TECHNICAL PRESENTATION XC9500XL CPLDs TECHNICAL PRESENTATION

XC9500XL Overview Superset of XC9500 CPLD Optimized for 3.3V systems compatible levels with 5.0/2.5V High fMAX = 200 MHz Fast tPD = 4 nsec Best ISP/JTAG support Best pin-locking Advanced packaging

Agenda Overview Technology Architecture Timing ISP Electrical Compatibility Support Family

XC9500XL Features Each macrocell independently selects clock source and phase inversion Clock enable at each macrocell Hysteresis on all inputs Pull-up/bus-hold option on pins at power on Extra-wide function block inputs

Technology Optimized for high speed 3.3V systems Leading-edge FLASH technology 0.35um feature-size (0.25um Leff) 4 layers of metal Superior reliability Reprogramming endurance = 10,000 Charge retention = 20 years Fast programming characteristics

Flash vs E2 Endurance Flash delivers: - highest quality - no speed degradation - 20 year retention - reliable reprogramming - worry free field upgrade

XC9500XL Architecture Uniform architecture Identical function blocks Identical macrocells Identical I/O pins Abundant global/product term resources Optimized synthesis results Superior pin-locking characteristics

High Level Architecture

FastCONNECT II Switch Matrix Very high speed switch matrix Greater connectability for all signals High routability at high utilization Software delivers high speed automatically Substantial power reduction

XC9500XL Function Block 54 Inputs Highest FB Fanin

XC9500XL Macrocell

Cascading 3 available here 2 p-terms required here 5 available here 5 native p-terms Total = 18 requires 2 cascade times added to tPD 5 available here

Timing

Timing Example 1 tOUT tIN tPDI + tLOGI tPD = tIN + tPDI + tLOGI + tOUT Function Block tOUT tIN tPDI + tLOGI tPD = tIN + tPDI + tLOGI + tOUT

Timing Example 2 tIN tPTA A tOUT B tLOGI + tPDI Function Block A tPTA tOUT B tLOGI + tPDI t A-> B = tIN + tPTA + tLOGI + tPDI + tOUT

Timing Example 3 tGCK tHI tSUI tSU = tIN + tLOGI + tSUI - tGCK Q D/T tGCK tHI tSUI GCK tSU = tIN + tLOGI + tSUI - tGCK tCO = tGCK + tCOI + tOUT tH = tGCK + tHI - tIN - tLOGI

ISP Original XC9500 JTAG and ISP instructions New instruction: CLAMP permits pin by pin definition of logic level Added S/W support with XACT M1.5 Same third party and ATE support package as XC9500 CPLDs (HP, GenRAD, Teradyne)

Voltage Compatibility VCCINT = 3.3V VCCIO = 3.3V/2.5V CORE LOGIC Note: output p-channel gives full rail swing

Voltage Compatibility 3.3V/5V VCCIO VCCINT 5V 3.3V Any Any XC9500XL 3.3V 5V TTL 3.3V 3.3V device device

Voltage Compatibility 3.3V/2.5V VCCIO VCCINT 3.3V 2.5V Any Any 3.3V XC9500XL 2.5V 2.5V 2.5V device device

XC9500XL Voltage Compatibility Summary  EIA Standard Voltage Levels  No Power Supply Sequencing Restriction

Input Signal Hysteresis VOH 50 mV VOUT (VOLTS) VOL 1.45V 1.40V VIN (VOLTS)

Power Optimization 67% decrease from 5V CPLDs Low power option per macrocell Even lower power if I/Os swing 0-2.5V FastCONNECT II lower power than XC9500 I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)

XC9500XL Design Software XC9500XL Fitters in all Xilinx Standard S/W Packages Foundation M1.5 Alliance M1.5 Support for Schematics, Verilog, VHDL, Abel Exemplar Synopsys Synplicity more

Third Party ATE Support Hewlett-Packard Teradyne Gen-RAD Common Support for both Xilinx FPGAs and CPLDs.

XC9500XL Family

The Next Generation CPLD Leadership speed - 4ns/200MHz Powerful new architecture Highest programming reliability FastFLASH technology