A. Stammermann, D. Helms, M. Schulte OFFIS Research Institute Binding, Allocation and Floorplanning in Low Power High-Level Synthesis A. Stammermann, D. Helms, M. Schulte OFFIS Research Institute A. Schulz, W. Nebel Univ. Of Oldenburg

Optimization Algorithm Evaluation Results Conclusion Outline Motivation Background Optimization Algorithm Evaluation Results Conclusion 11.11.2003 ICCAD 2003

Pdyn =  C VDD2 f Motivation Within actual CMOS-technologies (0.1m) 80-95% of the power consumption emerges from charging and discharging capacitances. VDD Input Output Switching activity  Capacitance of • gates at the output • connecting wires C GND Pdyn =  C VDD2 f Optimization target 11.11.2003 ICCAD 2003

Capacitance Distribution (ITRS Roadmap 2001) Increasing share of interconnect capacitance  Interconnect has to be considered during high-level synthesis. 11.11.2003 ICCAD 2003

Summary Capacitance contributes linear to power dissipation Wire capacitance is increasing Wire capacitance is dominated by its length  Thus it is important that accurate physical information is used during high-level synthesis 11.11.2003 ICCAD 2003

Chip Design RT-netlist Generation Gate-netlist Generation detailed Floorplanning ASIC-Cells rough Floorplanning RT-netlist Generation adder, multiplier Gate-netlist Generation Increasing level of details Floorplanning ASIC-Cells Interconnect 11.11.2003 ICCAD 2003

RT-Netlist Generation cstep 1 cstep 2 cstep 3 cstep 4 +1 +2 +3 +5 +4 Scheduling When are operations executed +1 +2 +3 +5 +4 Allocation How many resources Binding Which operation is executed on which resource +1 +2 +3 +5 +4 11.11.2003 ICCAD 2003

RT-Netlist Generation +1 +2 +3 +5 +4 +1 +2 +3 +5 +4 Reg1 Reg2 Reg3 Reg1 Reg2 Reg3 ADD1,2 ADD3 ADD4,5 ADD1 ADD2,3 ADD4,5 11.11.2003 ICCAD 2003

Impact on Power Dissipation Binding/Allocation Interleaving changes the characteristic of input streams: The switching activity  at the input of resources (and according wires) can increase or decrease. Influences netlist topology: The wire length resp. capacitance can increase or decrease. 1 +2 +1 ADD 11.11.2003 ICCAD 2003

Power Estimation Switching activity Simulation of behaviour description Power consumption of resources (e.g. adder) Power models Wire capacitance Capacitance model Floorplan 11.11.2003 ICCAD 2003

Floorplanning Slicing Floorplans Standard Supports softmacros (leafs are flexible in their aspect-ratio) Efficient representation as binary tree x y vertical + 1 * 4 2 3 5 2 4 1 3 5 horizontal 11.11.2003 ICCAD 2003

Optimization Algorithm Power optimization algorithm for RT-level netlist with regard to interconnect power Performs simultaneoulsy Slicing-tree structured based floorplanning Functional unit binding and allocation Changes in the netlist topology are mended immediately in the actual floorplan In contrast to previous approaches a generation from scratch is not necessary Non-deterministic, iterative optimization technique Simulated Annealing Cost function: PFE + PInter + Area 11.11.2003 ICCAD 2003

Simulated Annealing based floorplanner Floorplan moves Floorplan-Annealing Simulated Annealing based floorplanner Floorplan moves F1: Exchange two leafs F2: Exchange leaf and node F3: Change direction F4: Exchange two nodes F5: Displace a leaf / node 2 3 1 4 * + 2 3 1 4 F2: Exchange leaf and node * + 2 3 4 1 2 3 4 1 11.11.2003 ICCAD 2003

Floorplan-Annealing Initial Floorplan Floorplan move Fi new costs < old costs random number < e-Cost/T Undo move Fi N N Y Y Y Stopping criteria met? N Y Optimized floorplan 11.11.2003 ICCAD 2003

Architecture-Annealing Architecture moves (mutate binding/allocation) A1: Share Merge two resources res1 and res2 to one single resource res1 und res2 must be instances of the same type (e.g. ripple adder) A2: Split Inverse of Share Split a single resource into two resources A3: Swap Swap the inputs of commutative operations A1-A3 in combination are able to create every possible binding solution 11.11.2003 ICCAD 2003

Architecture-Annealing Changes in the architecture are mended immediately in the actual floorplan. Moves A1-A3 may cause resources to vanish or appear. Moves A1-A3 changes the netlist topology.  The floorplan is not optimal anymore after a move A1-A3. Solution: Each move A1-A3 is followed by a floorplan update (annealing). Supporting softmacros. Optimal inserting of new resources into floorplan. 11.11.2003 ICCAD 2003

Algorithm e-Cost/T Initial architecture/floorplan solution Each architecture move is followed by a floorplan-annealing Architecture move Aj floorplan- annealing new costs < old costs random number < e-Cost/T Undo move Aj Undo floorplan update N N Y Y Stopping criteria met? Optimized architecture/floorplan solution N Y 11.11.2003 ICCAD 2003

Inserting new resources 1 2 3 4 new softmacros hardmacros 1 2 3 4 new 8.2 LE 4.6 LU best position 1 2 3 4 11.11.2003 ICCAD 2003

Evaluation 3 experiments are performed: Full parallel Each operation is mapped on one single resource (no resource sharing). Consecutive Binding optimization and floorplan optimization are executed consecutively. This interconnect unaware optimization is similarly to the traditionally procedure in high-level synthesis. Simultaneous Binding and floorplanning is optimized simultaneously. 11.11.2003 ICCAD 2003

Results 11.11.2003 ICCAD 2003

Conclusion Compared to consecutively (traditionally) procedure the proposed technique reduces interconnect power almost by half increases the functional unit power insignificantly The CPU times vary from 6 seconds (diffeq) to 138 seconds (turbo_decoder). [1,0 GHz Athlon™ based PC with 256 MB memory] 11.11.2003 ICCAD 2003

Thank You! 11.11.2003 ICCAD 2003

Capacitance model Capacitance extracted from layout vs. capacitance from our model (0,35 m) 11.11.2003 ICCAD 2003

ITRS Roadmap 2001 International Technology Roadmap for Semiconductors 11.11.2003 ICCAD 2003

Cross Section on Die 11.11.2003 ICCAD 2003