Scalable Don’t-Care-Based Logic Optimization and Resynthesis Alan Mishchenko, University of California, Berkeley Robert Brayton, University of California, Berkeley Jie-Hong Roland Jiang, National Taiwan University Stephen Jang, Xilinx, Inc

Outline Motivation Brief history of don’t-cares Algorithm overview Algorithm components Experimental results Conclusion

Motivation Network after mapping Optimized network resynthesis  Applications tech-independent synthesis post-mapping delay/area optimization placement-aware resynthesis Requirements substantial logic restructuring flexibility to solve many optimization tasks reasonable runtime for large designs Our solution SAT-based re-synthesis with don’t-cares using resubstitution

Brief History of Don’t-Cares Previous century work (1960-2000) Permissible functions (Saburo Muroga, 1989) Compatible observability don’t-care (Hamid Savoj, 1992) Complete rather than compatible don’t-cares (2002) SAT-based don’t-care computation (2005) Interpolation-based optimization with don’t-cares without explicitly computing don’t-cares (this talk)

Background Summary Assuming familiarity with Networks and nodes Cuts and cones Don’t-cares and resubstitution SAT-based interpolation

Resubstitution with Don’t-Cares Consider all or some nodes in Boolean network For each node Create window Select possible fanin nodes (divisors) For each candidate subset of divisors Rule out some subsets using simulation Check resubstitution feasibility using SAT Compute resubstitution function using interpolation A low-cost by-product of completed SAT proofs Update the network, if there is an improvement

Resubstitution Resubstitution considers a node in a Boolean network and expresses it using a different set of fanin nodes X X Computation can be enhanced by don’t cares

Windowing a Node in the Network for Don’t-Care Computation Boolean network (k-LUT mapped circuit) Definition A window for a node in the network is the context in which the don’t-cares are computed A window includes n levels of the TFI m levels of the TFO all re-convergent paths captured in this scope Window with its PIs and POs can be considered as a separate network Window POs Window PIs n = 3 m = 3

Don’t-Care Representation Miter for don’t-care computation If output is 1, input is a care If output is 0, input is a don’t-care … Same window with inverter Window f f

Resubstitution with Don’t Cares Given: node function F(x) to be replaced care set C(x) for the node candidate set of divisors {gi(x)} for expressing F(x) Find: A resubstitution function h(y) such that F(x) = h(g(x)) on the care set SPFD Theorem: Function h exists if and only if each pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i C(x) F(x) g1 g2 g3 C(x) F(x) g1 g2 g3 h(g) F’(x)

Checking Resubstitution using SAT Miter for resubstitution check h(g) SPFD Theorem in practice Comments: Note use of care set, C. Resubstitution function exists if and only if the SAT problem is unsatisfiable Function h(g) is computed using interpolation

Experimental Setup Implemented in ABC (command “mfs”) The SAT solver is a modified version of MiniSat-1.14C, by Niklas Een and Niklas Sorensson The algorithm was applied to a mapped network and attempted resubstitution for each LUT to reduce (a) area, (b) number of fanins. Experiments targeting networks after FPGA mapping into 6-LUTs on an Intel Xeon 2-CPU with 8Gb of RAM The resulting networks have been verified using equivalence checker in ABC (command “cec”) Optimization scripts used Baseline: result of (dc2 –l; dc2 –l; if –C 12)1 Choices: best result of (st; dch; if –C 12)4 Mfs: best result of (st; dch; if –C 12; mfs –W 4)4

Results for Academic Benchmarks Example Profile Baseline Choices Mfs   PI PO FF LUT Level Time alu4 14 8 845 5 0.46 786 2.23 499 15.53 apex2 39 3 987 6 0.53 922 5.80 674 33.71 apex4 9 19 821 0.41 798 2.10 16.41 bigkey 263 197 224 567 0.60 0.86 455 1.68 clma 383 82 33 3309 10 1.80 2910 16.23 701 7 122.24 des 256 245 880 0.62 872 4 2.90 638 7.88 diffeq 64 377 712 0.37 690 0.80 645 2.77 dsip 229 682 0.50 681 0.58 677 2 1.65 elliptic 131 114 1122 1877 0.85 1914 2.20 1813 4.80 ex1010 2934 1.48 2712 17.14 1342 101.13 ex5p 63 593 521 1.58 119 4.57 frisc 20 116 886 1777 12 1.06 1749 7.43 1757 11 16.64 i10 257 595 0.39 554 1.37 545 9.35 misex3 772 0.43 2.19 368 12.11 pdc 16 40 2113 1.35 1959 15.36 128 25.91 s38417 28 106 1636 2257 1.33 2271 7.09 2206 26.11 s38584 278 1452 2319 1.47 2373 8.41 2250 14.01 seq 41 35 834 4.64 684 17.73 spla 46 1622 1.08 1417 11.58 161 19.12 tseng 52 122 385 717 0.30 0.63 639 2.35 Ratio 1.000 0.952 0.976 4.831 0.550 0.878 17.101 0.578 0.900 3.540

Results for Industrial Benchmarks Example Profile Baseline Choices Mfs PI PO FF LUT Lev Time Design01 1332 5064 5625 15453 8 10.08 14830 62.17 13793 7 104.91 Design02 1559 5701 10373 28091 10 21.50 26972 9 134.89 24997 312.14 Design03 993 5533 6430 15033 7.43 14428 40.69 14010 118.00 Design04 974 1301 940 2841 31 2.09 2723 30 7.82 2697 121.33 Design05 101 198 1177 2649 6 1.60 2554 5 10.86 2222 20.80 Design06 68 85 1355 3624 19 2.53 3385 16 27.58 3192 15 102.77 Design07 6598 11151 22382 71637 17 61.73 69747 475.84 63116 13 1154.14 Design08 2126 6451 7075 20504 12.27 19860 14 70.61 18943 12 150.09 Design09 2450 4798 3725 9951 4 3.13 9718 9.50 9374 3 21.67 Design10 1032 1767 1124 4447 2.24 4299 15.13 4105 44.32 Design11 4040 9406 35654 83113 71.99 81601 472.68 73478 1748.12 Design12 115 264 2293 5413 3.53 5209 24.07 4576 49.35 Design13 56 87 465 1756 1.19 1311 8.19 1162 27.44 Design14 60 426 1448 0.91 1455 8.79 1382 34.77 Ratio 1.000 1.00 0.949 0.90 6.310 0.882 0.83 18.801 0.930 0.92 2.979

Conclusion Introduced a new SAT-based logic optimization engine uses rugged windowing scheme without previous limitations uses SAT solver for all aspects of functional manipulation designed for scalability and applicable to large industrial circuits Showed promising experimental results academic benchmarks (10-40% in area, 10% in delay) industrial benchmarks (7% in area, 8% in delay) improvements can be made even on top of strong synthesis Future work improving runtime by fine-tuning simulation and SAT experimenting with timing-driven and power-aware resynthesis extending don’t-care computation to work with white-boxes global circuit restructuring using interpolation

The End

Algorithm Overview nodeSatBasedResynthesis( node, parameters ) { window = nodeWindow( node, parameters ); divisors = nodeDivisors( node, window, parameters ); cands = nodeResubCandsFilter( node, window, parameters ); best_cand = NULL; for each candidate set c in cands if ( best_cand != NULL && resubCost(best_cand) < resubCost(c) ) continue; if ( !resubFeasible( node, window, c ) ) best_cand = c; } if ( best_cand != NULL ) { best_func = nodeInterpolate( sat_solver, node ); nodeUpdate( node, best_cand, best_func );

Divisor Selection Divisor is a candidate fanin of the pivot node after resubstitution Divisor computation: Partition window PIs into (a) those in the TFI node of the pivot (b) the remaining window PIs Add nodes between the pivot and window PIs of type (a), excluding the node and the node’s MFFC Add nodes in the window if their structural support has no window PIs of type (b) Do not collect divisors whose level exceed a limit Do not collect more than a given number of divisors Window POs m = 3 Pivot node k = 3 type (b) type (b) type (a) Window PIs

Resubstitution Resubstitution of F(x) with care set C(x) and candidate functions {gi(x)} exists iff every pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i That is, if information of F(x) does not exceed that of {gi(x)} Example: Given F = (a  b)(b  c), C = 1 Two candidate sets: {y1= a’b, y2 = ab’c}, {y3= a  b, y4 = bc} Set {y1, y2} is feasible Set {y3, y4} is infeasible Counter-example: x1 = 100, x2 = 101 abc F y1 y2 y3 y4 000 001 010 1 011 100 101 110 111

Computing Dependency Function Definition of the interpolant: Consider A(x, y) and B(y, z), such that A(x, y)  B(y, z) = 0, where x and z appear only in the clauses of A and of B, respectively, and y are variables common to A and B. An interpolant of function A(x, y) w.r.t. function B(y, z) is a Boolean function, I(y), depending only on the common variables y, such that A(x, y)  I(y) and I(y)  (y, z). Problem: Find function h(g), such that h(g(x)) can replace f(x) on care set C(x), that is, C(x)  [h(g(x))f(x)]. The dependency function h(g) expresses the node, f(x), in terms of {gi}. Solution: Prove the corresponding SAT problem “unsatisfiable” Derive unsatisfiability proof [Goldberg/Novikov, DATE’03] Derive interpolant from the unsatisfiability proof using McMillan’s procedure [CAV’03] (assume A and B as shown on previous slide) Use interpolant as the dependency function, h(g)

Resynthesis Heuristics Resynthesis is attempted for each node Window, divisors, and resubstitution candidates are computed Heuristics for different minimization criteria: Area Try replacing each fanin whose reference counter is 1 Fanin count Try replacing each fanin Delay Try replacing each fanin that is on the critical path

Previous Work Optimization and mapping with internal flexibilities S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, “The transduction method-design of logic networks based on permissible functions”, IEEE Trans. Comp, Vol.38(10), pp. 1404-1424, Oct 1989 H. Savoj. Don't cares in multi-level network optimization. Ph.D. Dissertation, UC Berkeley, May 1992. V. N. Kravets and P. Kudva, “Implicit enumeration of structural changes in circuit optimization”, Proc. DAC ’04, pp. 438-441. A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", Proc. DATE '05, pp. 418-423. K. McMillan, “Don't-care computation using k-clause approximation”, Proc. IWLS ’05, pp. 153-160. Equivalence under don’t-cares Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli. "SAT sweeping with local observability don't-cares," Proc. DAC ’06, pp. 229-234. S. Plaza, K.-H. Chang, I. L. Markov, and V. Bertacco, “Node mergers in the presence of don't cares'', Proc. ASP-DAC’07, pp. 414-419. Maximal reduction resynthesis without don’t-cares K.-C. Chen and J. Cong, “Maximal reduction of lookup-table-based FPGAs”, Proc. DATE ’92, pp. 224-229. Computing dependency functions using interpolation C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko. “Scalable exploration of functional dependency by interpolation and incremental SAT solving”, Proc. IWLS’07.

Experimental Results Implementation of SAT-based resynthesis ABC: Logic synthesis and verification system developed at UC Berkeley SAT solver used is MiniSat-C_v1.14.1 by Niklas Een and Niklas Sörensson Outline of experiments Perform technology-independent synthesis: resyn; if Perform high-quality FPGA mapping: if Perform resynthesis without choices: imfs –W 66; imfs –a –W 66; imfs -W 66 with choices (script is more complicated) Measure gain in area, delay, net count Commands used in the scripts if is a new efficient FPGA mapper based on priority cuts imfs is the new logic optimization and resynthesis engine described in the present paper, resyn is a fast logic synthesis script that performs 5 iterations of AIG rewriting, choice is a logic synthesis script that performs 15 passes of AIG rewriting and collects three snapshots of the current network: the original, the final, and an intermediate AIG saved after the first 5 rewriting passes. Computer used ? Runtime is several minutes for the largest designs in the tables

Academic Benchmarks

Academic Benchmarks (PLAs)