CS 140L Lecture 1 Professor CK Cheng 10/2/02.

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Presentation transcript:

CS 140L Lecture 1 Professor CK Cheng 10/2/02

Behavior description C, System C, Verilog, VHDL Register Transfer Level Verilog, VHDL Logic Synthesis Netlist of Logic Logic Diagram Placement, Routing Physical Layout Mask Fabrication FPGAs Data representation Progress, Design Automation Analysis: Functional, Timing

FPGAs (Field Programmable Gate Arrays) Programmable Logic Block Switches Switch Matrix Wiring Channels -SRAM based (Flash memory) -antifuse Disadvantages: Penalty on area, density, speed Advantages: Flexibility, low startup costs, low risk, revisions without changing the hardware

CMOS Logic (3.2 – 3.6) Complementary Metal-Oxide Semiconductor

1. Transistors (FET) Field Effect Transistor G NMOS G W L D S S G =1 => D =S { D = 1 => S = 0.8 D = 0 => S = 0 G = 0 => D&S are separated.

D G L W r c WxL , C D S C G PMOS A B S C ’ G = 1 => D&S are separated. G = 0 => D =S { D = 1 => S = 1 D = 0 => S = 0.2