Øyvind Hagen Senior Hardware Developer Introduction To Qsys Øyvind Hagen Senior Hardware Developer 7/16/2019

Introduction to Qsys Agenda Qsys Integration Tool Creating a System What does it do Qsys and Megawizard Tool Overview Creating a System A basic system with clock and reset Adding components to the system Making connections between components Taking a closer look at the Qsys interconnect Generating synthesis and simulation files Making a Component Adding synthesis and simulation files and selecting the top-level file Defining interfaces using signals in the top-level file Hardware Component Description File (_hw.tcl) Generated Files and Scripting Synthesis files and inclusion in an existing Quartus II project Simulation files and setup for Modelsim Version control and scripting Further Reading 7/16/2019

Qsys Integration Tool Qsys Integration Tool What does it do Create subsystems using IP from Altera, third party or custom Automatically generate interconnect (clock domain crossing, bus width adaption, address decoding, arbitration, bus standard conversion, etc.) Automatic code generation (VHDL/Verilog) for synthesis and simulation Qsys and Megawizard Qsys is a replacement for SOPC builder SOPC builder was used for developing embedded Nios II (soft processor) systems The IP Parameter Editor, which is new in Quartus 14.0, is powered by Qsys Tool Overview Start it from Tools->Qsys or IP catalog Highly modular Automatically adds Qsys interconnect to design when needed Uses command line tools for automatic code generation 7/16/2019

Creating a System Creating a System A basic system with clock and reset Clock and reset are exported Adding components to the system Select from IP catalog Create custom components which can be added Making connections between components Connect interfaces internally or export them Matching interface types can be connected Taking a closer look at the Qsys interconnect Automatic generation of interconnect View a system with interconnect Assigning base addresses Generating synthesis and simulation files 7/16/2019

Making a Component Making a Component Adding synthesis and simulation files and selecting the top-level file Qsys only supports std_logic and std_logic_vector for ports Generics will be added as parameters Defining interfaces using signals in the top-level file Define standard interfaces and add signals to the interfaces Conduit interfaces can be used for arbitrary signals Hardware Component Description File (_hw.tcl) Contains definitions for Qsys components All IP components in Qsys are accompanied by a _hw.tcl file 7/16/2019

Generated Files and Scripting Synthesis files and inclusion in an existing Quartus II project Generate HDL for synthesis and include QIP file in project Simulation files and setup for Modelsim Generate HDL for simulation and run msim_setup.tcl for Modelsim Version control and scripting Only store the .qsys file in version control (all other files are automatically generated) Environment variables: QUARTUS_ROOTDIR and QSYS_ROOTDIR (points to QUARTUS_ROOTDIR/sopcbuilder/bin) ip-generate and ip-make-simscript from QSYS_ROOTDIR (see output from Generate HDL is Qsys for parameters) For synthesis set ::quartus(qip_path) and include the generated .qip file For simulation using Modelsim. Set ::QSYS_SIMDIR and create some of the libraries (everything except precompiled device libraries) in the msim_setup.tcl file and run “com” to compile the design and then “elab” to start simulation 7/16/2019

Further Reading Further Reading Qsys System Integration Tool Support: http://www.altera.com/support/software/system/qsys/sof-qsys-index.html Qsys System Design Tutorial: http://www.altera.com/literature/tt/tt_qsys_intro.pdf Embedded Peripheral IP User Guide: http://www.altera.com/literature/ug/ug_embedded_ip.pdf Introduction to Avalon Verification IP Suite: http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf 7/16/2019

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