ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing

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ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12 Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Clock Distribution clock Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Clock Power Pclk = CLVDD2f + CLVDD2f / λ + CLVDD2f / λ2 + . . . stages – 1 1 = CLVDD2f Σ ─ n= 0 λn where CL = total load capacitance λ = constant fanout at each stage in distribution network Clock consumes about 40% of total processor power. Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Delay of a CMOS Gate Intrinsic capacitance Gate capacitance CMOS gate Cg Cint CL Propagation delay through the gate: tp = 0.69 Req(Cint + CL) ≈ 0.69 ReqCg(1 + CL /Cg) = tp0(1 + CL /Cg) Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

Req, Cg, Cint, and Width Sizing Req: equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor Cg: gate capacitance, proportional to CoxWL; scales as S Cint: intrinsic output capacitance ≈ Cg, for submicron processes tp0: intrinsic delay = 0.69ReqCg; independent of sizing Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Effective Fan-out, f Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f = CL/Cg tp = tp0(1 + f ) Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

Sizing an Inverter Chain 1 2 N Cg1 Cg2 CL Cg2 = f2Cg1 tp1 = tp0 (1 + Cg2/Cg1) tp2 = tp0 (1 + Cg3/Cg2) N N tp = Σ tpj = tp0 Σ (1 + Cgj+1/Cgj) j=1 j=1 Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Minimum Delay Sizing Equate partial derivatives of tp with respect to Cgj to 0: 1/Cg1 – Cg3/Cg22 = 0, etc. or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance is geometric mean of forward and backward gate capacitances. Also, Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N) Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Minimum Delay Sizing Equate partial derivatives of tp with respect to N to 0: dNtp0(1 + F1/N) ───────── = 0 dN i.e., F1/N – F1/N(ln F)/N = 0 or ln F1/N = ln f = 1 → f = e = 2.7 and N = ln F Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Section 5.4. Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Summary Device sizing combined with supply voltage reduction reduces energy consumption. For large fan-out energy reduction by a factor of 10 is possible. An exception is F = 1 case, where the minimum size device is also the most effective one. Oversizing the devices increases energy consumption. Spring 2012, Mar 5 ELEC 7770: Advanced VLSI Design (Agrawal)