The George Washington University High-Level Programming of High-Performance Reconfigurable Computers: MAPLD BOF-H2 Panel Tarek El-Ghazawi The George Washington University tarek@gwu.edu http://www.seas.gwu.edu/~tarek

The Question and My Answer "Can we develop a software-level programming approach (e.g., a C language compiler) for FPGAs that spans the needs of the high performance reconfigurable computing community with a multitude of FPGA-based HPC systems and also the needs of the electronic design automation community with a multitude of FPGA board designs? My Answer: You Bet!

HOW? Abstraction Design a rich programming model for high-performance reconfigurable machines Extend a standard sequential language to conform to the programming model view Compilers to address common architectural features Run-time systems to tune to specific machine features

Programming Models for Parallel Computers Process/Thread Address Space Data Parallel e.g. HPF, C* Message Passing Shared Memory DSM/PGAS Ex: MPI[e.g. +C] Ex: OpenMP[e.g.+C] Ex: UPC

How cont.! Avoid the hype! Need to know that it is hard, will take enormous time and resources, but REALLY WORTH IT! Needed Efforts Need abstract programming model(s) to express fine grain data parallelism and coarse grain functional parallelism multiple levels of locality Need automatic H.W./S.W partitioning and scheduling algorithms Need compilers to address automatically general hardware optimizations and use reconfiguration to achieve them Need run-time systems to support further machine specific tunings Need H.W./S.W. debuggers and performance analysis tools And a lot more!!! But the good news are: There are solid intermediate steps There are works in related areas that can be leveraged