COSC 3330/6308 Materials on the Final Jehan-François Pâris December 2012

Chapter V Processor Architecture You are responsible for Data paths for individual MIPS instructions Pipelining and pipelining hazards You are not responsible for Control signal implementation Exceptions and Interrupts These topics are specifically excluded

Chapter VI The Memory Hierarchy You are responsible for Caches Cache consistency You are not responsible for Anything else in the chapter These topics are specifically excluded

Chapter VII Storage and I/O You are responsible for Most of the chapter except for the topics that were not covered in the slides You are not responsible for Storage class memories This topic is specifically excluded

Chapter VIII Parallel Processor architecture You are responsible for Whole chapter except for the topics that were not covered in the slides Recall that I covered in some detail hardware multithreading

Appendix A GPUS You are responsible for Contents of the slides except descriptions of individual systems and GPUs Focus on the big picture, CUDA and barriers

Overall tips I like to ask Numerical problems Questions on advantages and disadvantages of various solutions Questions about instruction data paths All topics that are not discussed in the slides are excluded.

Exam Organization One question on the data paths for a specific instruction (as in the midterm) One question about hazards One or two small problems about caches One or two small problems about system availability system reliability and RAIDs A few true or false questions with a catch You will have to explain your answer