IP Reuse through Machine Learning Center Proprietary IP Reuse through Machine Learning Yi Wang, Weiyi Qi, Brian Floyd and Paul Franzon Problem Statements Machine Learning-based Method Flow Overview Mixed signal circuit system IP optimization & technology node migration Modern complex system design requires time-consuming simulation Purely optimization-based method no longer fits complex system optimization problem We propose a hybrid methodology and apply it on SERDES 1st Phase: SERDES Receiver IP Design Behavioral Level Model Build and Optimization SPICE Netlist Generation based on Optimized Behavioral Model 2nd Phase: Mixed Signal IP Migration from one node to another Two components: design analysis and design optimization IP reuse is done by optimizing the same topology in the target node Goals and Outcomes Design Analysis: Parameter Screening: analyze the design parameters and remove unimportant ones Method Applied: PCCA(Pearson Correlation Coefficient Analysis) And PCA(Principle Component Analysis) Design Optimization: Surrogate models constructed with mixed method of Kriging Model with Gaussian Correlation Function and Multivariate Adaptive Regression Spline, the tool uses DDS (Dynamically Dimensioned Search) algorithm to efficiently find global optimal design parameter values. A tool and methodology that perform efficient high level design analysis and permit IP to be reused at SPICE level from one technology to another, including: Tools for efficient system level design optimization and IP reuse Tools for porting high level parameters to circuit component size for SPICE Optimization Flow: System to Be Studied High Level SerDes Receiver Design: Initial experiment design Iterate until stop criterion met Costly function evaluation in step 1 Use new sample to update response surface Fit response surface to predict objective function Use response surface to do next sample & evaluation SERDES Optimized Behavioral Design Block Python Package Implementation (BOCO) We are developing the code of in this project into a Bayesian Optimization Circuit Optimizer (BOCO) python package. Key features: Easy to setup with intuitive API Extensible and generally applicable Use state-of-the-art open source libraries for best performance A snippet of the “problem” declaration: Mixed Signal Equalizer CDR PLL Current APIs include: BOCO.design_analysis(), BOCO.reduce_dimension(), and BOCO.optimize() Current status: 1st release expected by the end of Nov., 2017. More functionalities will be added, and will be ported and tested in the Linux system. SPICE Level Blocks to be ported Result & Future Work Simulation Configuration Initial Design: lhd with corner points Sample method: DDS Model Builder(Kernel): Mixture of Kriging and MARS Preliminary Tunable Design Parameters FFE Filter Taps a0_FFE [-2,2] a1_FFE a2_FFE a3_FFE FBE Filter Taps a0_FBE a1_FBE a2_FBE Integrator_CDR num(A*bit_rate) [1e-9,1e-7] den [1,10] lead/lag_CDR num(B*Ts) [200,400] den(C*Ts) [1,20] Design Objective Minimize Eye SNR CTLE DFE Future Plan Machine Learning Optimization Investigate Neural Network Inverse Modeling within frame of behavioral model Multi-Objectives Optimization Circuit Implementation Map high level model parameters to spice level component size Optimized Parameters: [0.5610,-0.2567,0.1073,-0.3418,0.4208,0.6868,-0.6851 9.63e-9,3.45,340.4,18.2] PLL Based CDR