Progress Report 2015/01/28.

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Presentation transcript:

Progress Report 2015/01/28

Project Goal Study the current scheduling algorithms for homogenous and asymmetric multi-core architecture. Design and implement the hypervisor scheduler on asymmetric multi-core platform. Assign virtual cores to physical cores for execution. Minimize the power consumption with performance guarantee.

In the Past Few Weeks… Build an asymmetry-aware scheduler in Xen on ARM Juno board. Testing and debugging Finish a version for ITRI Demo.

Current Status The scheduler works fine under ITRI demo scenarios. Can generate energy-efficient scheduling plan, and assign virtual cores to physical cores for execution according to the plan. ITRI demo scenario: Two VMs running light-weight workload. One VM with medium-weight workload, while the other with heavy workload.

Setting Each “master core” is dedicate to one vCPU from Dom0. Dom0 Guest (DomU) VCPU Guest1 (DomU) VCPU VCPU Xen Asymmetry-aware Scheduler Cortex-A57 Each “master core” is dedicate to one vCPU from Dom0. Cortex-A53 Cortex-A53 Cortex-A53 Cortex-A57 Cortex-A53

Results - Scenario 1 [Credit-base scheduler] [Asymmetry-aware scheduler]

Results - Scenario 2 [Credit-base scheduler] [Asymmetry-aware scheduler]

Experimental Results Energy (J = W* Sec) Time (Sec) [Case 1] Light Credit-based 13.104 23.6 7.38/13.104 = 0.563 Asymmetric-aware 7.38 24.6 [Case 2] Medium + Heavy 36.733 58.8 39.26/36.733 = 1.07 39.26 61.8 8

Overhead from Dom0

Experimental Results(Ideal) Energy (J = W* Sec) Time (Sec) [Case 1] Light Credit-based 13.104 23.6 4.428/13.104 = 0.338 Asymmetric-aware 4.428 24.6 [Case 2] Medium + Heavy 36.733 58.8 31.844/36.733 = 0.867 31.844 61.8 10

Benchmark Score(Iterations/Sec.) Guest 0 Guest 1 Case 1 Credit-based 1842.07 2955 Asymmetric-aware 1811.27 1793.51 Case 2 3653.41 5915.74 3651.52 5724.30 11

Next Paper submission (Feb. 6th) Reduce Dom0 overhead. Keep debugging. Complete the scheduling framework Fetching workload information from guest VM, cooperate with physical core DVFS mechanism ... etc.