Introduction to VLSI Programming Lecture 5: Tangram & Tools

Slides:



Advertisements
Similar presentations
Introduction to VLSI Programming TU/e course 2IN30 Lecture 2: Control Handshake Circuits (1) Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir. Ad.
Advertisements

Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.
التصميم المنطقي Second Course
Introduction to VLSI Programming TU/e course 2IN30 Lecture 3: Control Handshake Circuits (2)
Clockless Logic System-Level Specification and Synthesis Ack: Tiberiu Chelcea.
1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)
VLSI Programming of Asynchronous circuits for Low Power Kees van Berkel Philips Research Lab. Martin Rem Eindhoven University of Technology.
Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.
Introduction to asynchronous circuit design: specification and synthesis Part IV: Synthesis from HDL Other synthesis paradigms.
1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.
General information CSE 230 : Introduction to Software Engineering
Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs.
Introduction to VLSI Programming Lecture 6: Resource sharing (course 2IN30) Prof. dr. ir.Kees van Berkel.
CSE 322: Software Reliability Engineering Topics covered: Course outline and schedule Introduction, Motivation and Basic Concepts.
Unit 4 Review Solutions a 5 – 32a 2 4a 2 (3a 3 – 8) 2. a 2 b 2 + ab ab(ab + 1) 3. x(x – 2) + y(2 – x) x(x – 2) – y(x – 2) (x – 2)(x – y)
Introduction to Silicon Programming in the Tangram/Haste language Material adapted from lectures by: Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir.
Introduction to Silicon Programming in the Tangram/Haste language Material adapted from lectures by: Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir.
FACTORING ALGEBRAIC EXPRESSIONS
Technical Report Writing and Presentation Skills Course Outline 1.
Fall 08, Oct 29ELEC Lecture 7 (updated) 1 Lecture 7: VHDL - Introduction ELEC 2200: Digital Logic Circuits Nitin Yogi
Nov. 20, 2010 A pessimistic one-step diagnosis algorithms for cube-like networks under the PMC model Dr. C. H. Tsai Department of C.S.I.E, National Dong.
CPSC 321 Introduction to Logic Circuit Design Mihaela Ulieru (‘Dr. M’)
E&CE % Final 30% Laboratory 20% Midterm ON LINE Course Notes! Lab Manual LabTechs/TAs Assignments extra probs/solns.
Chapter 5 Factoring and Algebraic Fractions
Lesson 3 Menu Five-Minute Check (over Lesson 7-2) Main Ideas and Vocabulary Targeted TEKS Example 1: Identify Polynomials Example 2: Write a Polynomial.
ELEC692/04 course_des 1 ELEC 692 Special Topic VLSI Signal Processing Architecture Fall 2004 Chi-ying Tsui Department of Electrical and Electronic Engineering.
CSE 171 Introduction to Digital Logic and Microprocessors Prof. Richard E. Haskell 115 Dodge Hall.
Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.
Market Systems Release Update Modifications Committee Meeting 55 June 19 th
COMPILER CONSTRUCTION Lesson 1 – TDDD16 TDDB44 Compiler Construction 2010 Kristian Stavåker (Erik Hansson.
10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt Midsegments.
CEN 283 Digital Design Assoc. Prof. Dr. Abdülhamit Subaşı Nejdet Dogru
Lecture 4 Introduction to Promela. Promela and Spin Promela - process meta language G. Holzmann, Bell Labs (Lucent) C-like language + concurrency dyamic.
FFF FFF i v e o r m s o f a c t o r i n g 1.Greatest Common Factor (GCF) Ex 1 10x 2 y 3 z - 8x 4 y 2 2x 2 y 2 (5yz - 4x 2 ) Ex 2 15a 2 b 5 + 5ab 2 -
Splash Screen. Lesson Menu Five-Minute Check (over Lesson 9–1) Then/Now Example 1:LCM of Monomials and Polynomials Key Concept: Adding and Subtracting.
Logic Gates Ghader Kurdi Adapted from the slides prepared by DEPARTMENT OF PREPARATORY YEAR.
BELL RINGER. MULTIPLYING A MONOMIAL BY A POLYNOMIAL.
Combinational Design, Part 2: Procedure. 2 Topics Positive vs. negative logic Design procedure.
Introduction to the FPGA and Labs
8.2A Factoring using Distributive Property
Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章(Chapter 58) 伏者潛藏也
ECE 301 – Digital Electronics
Synthesis from HDL Other synthesis paradigms
with Dr. Tracey Richardson Course Developer
F i v e o r m s o f a c t o r i n g For Forms 1 - 3, do the examples on your paper then use the PowerPoint to check your answers Do not do Form 4.
Part IV: Synthesis from HDL Other synthesis paradigms
FIGURES FOR CHAPTER 2 BOOLEAN ALGEBRA
Code Generation Part I Chapter 9
Introduction to VLSI Programming Lecture 9: High Performance DLX
Introduction to VLSI Programming Lecture 7: Introduction to the DLX
Code Generation Part I Chapter 8 (1st ed. Ch.9)
Computer Architecture and Design Lecture 6
Introduction toVLSI Programming Lecture 4: Data handshake circuits
Homework Questions.
Code Generation Part I Chapter 9
Introduction to VLSI Programming Lecture 8: High Performance (DLX)
Introduction to Silicon Programming in the Tangram/Haste language
Objectives The student will be able to:
Objectives The student will be able to:
Overview of Course Assessment National 3
Introduction to VLSI Programming Lecture 7: Introduction to the DLX
Instructor: Alexander Stoytchev
Introduction to VLSI Programming High Performance DLX
Objectives The student will be able to:
Homework Reading Machine Projects Labs
Factoring using the greatest common factor (GCF).
Objectives The student will be able to:
F i v e o r m s o f a c t o r i n g.
Introduction to Silicon Programming in the Tangram/Haste language
VHDL - Introduction.
Presentation transcript:

Introduction to VLSI Programming Lecture 5: Tangram & Tools (course 2IN30) Prof. dr. ir.Kees van Berkel

Time table 2005 date class | lab subject Aug. 30 2 | 0 hours intro; VLSI Sep. 6 3 | 0 hours handshake circuits Sep. 13 handshake circuits assignment Sep. 20 Tangram Sep. 27 no lecture Oct. 4 Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment Oct. 18 design cases; Oct. 25 DLX introduction Nov. 1 low-cost DLX Nov. 8 high-speed DLX Nov. 29 deadline final report 7/29/2019 Kees van Berkel

Lecture 5 Outline: Recapitulation Lecture 4 Tangram overview Compilation: Tangram Handshake Circuits Tools Demonstration Lab work: assignment “fifos and registers” 7/29/2019 Kees van Berkel

Handshake signaling and data request ar active side passive side acknowledge ak data ad push channel versus pull channel request ar active side passive side acknowledge ak data ad 7/29/2019 Kees van Berkel

Tangram assignment x:= f(y,z) yw zw y f z   xw0 | x xr xw1 y f z   y f z   | x | x Handshake circuit 7/29/2019 Kees van Berkel

Two-place wagging buffer  byte = type [0..255] & wag2: main proc (a?chan byte & b!chan byte). begin x,y: var byte | a?x ; forever do (a?y || b!x) ; (a?x || b!y) od end 7/29/2019 Kees van Berkel

Four 88 shift registers compared 7/29/2019 Kees van Berkel

Tangram/Haste Purpose: programming language for asynchronous VLSI circuits. Creator: Tangram team @ Philips Research Labs (proto-Tangram 1986; release 2 in 1998). Inspiration: Hoare’s CSP, Dijkstra’s GCL. Lectures: no formal introduction; manual hand-out (learn by example, learn by doing). Main tools: compiler, analyzer, simulator, viewer. 7/29/2019 Kees van Berkel

2-place buffer BUF1 a b c byte = type [0..255] & BUF1 = proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end & BUF2: main proc (a?chan byte & c!chan byte). begin b: chan byte | BUF1(a,b) || BUF1(b,c) end 7/29/2019 Kees van Berkel

Median filter median: main proc (a? chan W & b! chan W). begin x,y,z: var W & xy, yz, zw: var bool | forever do ((z:=y; y:=x) || yz:=xy) ; a?x ; (xy:= x<=y || zx:= z<=x) ; if zx=xy then b!x or xy=yz then b!y or yz=zx then b!z fi od end Median a b 7/29/2019 Kees van Berkel

Greatest Common Divisor gcd: main proc (ab?chan <<byte,byte>> & c!chan byte). begin x,y: var byte | forever do ab?<<x,y>> ; do x<y then y:= y-x or x>y then x:= x-y od ; c!x od end GCD ab c 7/29/2019 Kees van Berkel

Nacking Arbiter nack: main proc (a?chan bool & b!chan bool). begin na,nb: var bool | <<na,nb>> := <<true,true>> ; forever do sel probe(a) then a!nb || na:= na#nb or probe(b) then b!na || nb:= nb#na les od end Nacking arbiter a b 7/29/2019 Kees van Berkel

C : Tangram  handshake circuit  a b C(T) = ;  a c S R C(R;S)= 7/29/2019 Kees van Berkel

C : Tangram  handshake circuit ;  a c S R C(R;S)= a c S R ;  C(R;S)= | b 7/29/2019 Kees van Berkel

C : Tangram  handshake circuit ||   o | rx i C (R||S) = 7/29/2019 Kees van Berkel

Tangram Compilation Theorem Tangram program T Handshake circuit VLSI circuit C E Handshake process H ||  · H · T = || · C ·T 7/29/2019 Kees van Berkel

VLSI programming of asynchronous circuits behavior, area, time, energy, test coverage Tangram program feedback compiler simulator Handshake circuit expander Asynchronous circuit (netlist of gates) 7/29/2019 Kees van Berkel

Tangram tool box Let Rlin4.tg be a Tangram program: htcomp -B Rlin4 compiles Rlin4.tg into Rlin4.hcl, a handshake circuit htmap Rlin4 produces Rlin4*.v files, a CMOS standard-cell circuit htsim Rlin4 a b executes Rlin4.hcl with files a, b for input/output htview Rlin4 provides interactive viewing of simulation results 7/29/2019 Kees van Berkel

Tangram program “Conway” b Q c R d B1 = type [0..1] & B2 = type <<B1,B1>> & B3 = type <<B1,B1,B1>> & P = … & Q = … & R = … & conway: main proc (a?chan B2 & d!chan B3). begin b,c: chan B1 | P(a,b) || Q(b,c) || R(c,d) end 7/29/2019 Kees van Berkel

Tangram program “Conway” & P = proc(a?chan B2 & b!chan B1). begin x: var B2 | forever do a?x; b!x.0; b!x.1 od end & Q= proc(b?chan B1 & c!chan B1). begin y: var B1 | forever do b?y; c!y od end & R= proc(c?chan B1 & d!chan B3). begin x,y,z: var B1 | forever do c?x; c?y; c?z; d!<<x,y,z>> od end 7/29/2019 Kees van Berkel

Lab work: assignments 1 and 2 Assignment 1: shift registers Assignment 2: fifos See separate handout. 7/29/2019 Kees van Berkel

Lab-work and report You are allowed to team up with a colleague (Not mandatory.) Report: more than listing of functional Tangram programs: analyze the specifications and requirements; present design options, alternatives, trade-offs; motivate your design choices; explain functional correctness of your Tangram programs; analyze & explain {area, time, energy} of your programs. 7/29/2019 Kees van Berkel

Course grading Your course grading is based on: the quality of your Tangram programs; [30%] your final report on the design and evaluation of these programs (guidelines will follow); [30%] a concluding discussion with you on the programs, the report and the lecture notes; [20%] your results on an intermediate assignment. [20%] 7/29/2019 Kees van Berkel

Next time: lecture 6 (2005, Oct 17) Outline: Tangram: arithmetic & resource sharing Lab work: assignments on arithmetic & resource sharing 7/29/2019 Kees van Berkel