Advanced Computer Architecture Lecture 10 Project 3 reviews Project 4 introduction DMA controller Lillevik 437s06-l10 University of Portland School of Engineering

Project 3 team reviews Team Cat Team Dog Lillevik 437s06-l10 University of Portland School of Engineering

Project 4 overview Objective: design a round-robin arbiter for a four-CPU system System Contains four unique CPU models (CPU0, CPU1, CPU2, CPU3) and programs (pgm0, pgm1, pgm2, pgm3) Four bus requests (Breq0, Breq1, Breq2, Breq3) Four bus grants (Bgnt0, Bgnt1, Bgnt2, Bgnt3) Lillevik 437s06-l10 University of Portland School of Engineering

Project 4 system Arbiter Lillevik 437s06-l10 University of Portland School of Engineering

Arbiter similar to Grey code counter Project 4 state diagram 00 10 11 01 G B C D E F H A Arbiter similar to Grey code counter Lillevik 437s06-l10 University of Portland School of Engineering

Each CPU writes to Port 10, twice Project 4 program CPU0 NOTE: Addresses 0, 1 code will change for each CPU EXAMPLE: CPU 3 will execute 0xa1003 nop Each CPU writes to Port 10, twice Lillevik 437s06-l10 University of Portland School of Engineering

Find expected behavior? Zero gets bus first Writes 0 into Port 10 CPU 1 gets bus, writes 1 to Port 10 CPU 3 CPU 2 Lillevik 437s06-l10 University of Portland School of Engineering

Project 4 trace Lillevik 437s06-l10 University of Portland School of Engineering

Hard drive DMA Assumptions Initialization commands Project 5 Assumptions Operation: Input, or read disk, or read file HD buffer: represent with a ROM Initialization commands Port 1: start address Port 2: word count Port 4: start Design contains 5 sections Lillevik 437s06-l10 University of Portland School of Engineering

DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer System bus adr 0 adr (n-1) Lillevik 437s06-l10 University of Portland School of Engineering

HD system schematic Lillevik 437s06-l10 University of Portland School of Engineering

Memory schematic Lillevik 437s06-l10 University of Portland School of Engineering

DMA controller architecture Word Count Data Buffer Memory Address Control D A C Xcvr Counts up from zero Counts down to zero Preset counter Lillevik 437s06-l10 University of Portland School of Engineering

BA counts from zero up to N-1 Buffer address block Buffer Address BAclr BAdr BAinc BA counts from zero up to N-1 Lillevik 437s06-l10 University of Portland School of Engineering

Data buffer block BAdr Data Buffer (ROM) Data Ben Lillevik 437s06-l10 University of Portland School of Engineering

WC counts down from N-1 to zero Word count block Word Count WCload WCdec Zero Data WC counts down from N-1 to zero Lillevik 437s06-l10 University of Portland School of Engineering

MA counts up from X to X+(N-1) Memory address block Memory Address MAload MAinc Ben A D MA counts up from X to X+(N-1) Lillevik 437s06-l10 University of Portland School of Engineering

Updated block diagram Data Buffer Word Memory Count Address Xcvr D one section Word Count Data Buffer Memory Address Control D A C Xcvr Port1 Port2 BAclr BAinc WCdec MAinc Zero Ben Lillevik 437s06-l10 University of Portland School of Engineering

Control section Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done Role Contains three subsections: decoder, counters, bus I/F Bus I/F or FSM similar to CPU model Lillevik 437s06-l10 University of Portland School of Engineering

Control 1: decode Objective: respond to CPU (I/O write) commands Port 1: start address on D bus Port 2: word count on D bus Port 4: start (D bus ignored) Role: create signals to load the MA counter, load WC counter, start DMA Lillevik 437s06-l10 University of Portland School of Engineering

Control section block 1 Decode A Decode Port1 (MAload) Logic Port2 (WCload) C Port4 (Start) Lillevik 437s06-l10 University of Portland School of Engineering

Control 2: counters Objective: look for start signal, enter a sequence, repeat, stop when done (WC= =0) Role: manipulate the three counters (buffer address, word count, memory address) Lillevik 437s06-l10 University of Portland School of Engineering

Control section block 2 Counters Enables BAclr Start BAinc WCdec Zero One signal? Zero MAinc Lillevik 437s06-l10 University of Portland School of Engineering

Control 3: bus I/F Objective: request the bus, drive the bus with data, generate interrupt when done Role: Generate a sequence of Breq, Bgnt, Ben, Ack Drive the C, A, and D buses Drive the Int line and wait for Inta Lillevik 437s06-l10 University of Portland School of Engineering

Must drive C bus with memory write instruction Control section block 3 Bus interface Bus I/F Breq Bgnt Int Ack Ben Inta C Must drive C bus with memory write instruction Lillevik 437s06-l10 University of Portland School of Engineering

Control input/outputs? Lillevik 437s06-l10 University of Portland School of Engineering

HD DMA schematic Lillevik 437s06-l10 University of Portland School of Engineering

Lillevik 437s06-l10 University of Portland School of Engineering

Find expected behavior? All CPU’s request the bus at the same time Arbiter selects one CPU to own bus Arbiter issues bus grants in sequence {0, 1, 3, 2} First CPU to own bus depends on state of arbiter at that time Lillevik 437s06-l10 University of Portland School of Engineering

Control input/outputs? FSM Clk, Reset Breq Bgnt Zero Count Ben Inta Int Port4 Clear Ack Lillevik 437s06-l10 University of Portland School of Engineering