May 9, Platform Design Considerations Eric Rosario Intel Corporation

May 9, Agenda w Guidelines w Measurement Techniques w Testing Results w Summary

May 9, Guidelines w USB 2.0 guidelines are more systematic, detailed than 1.x whitepapers w The USB 2.0 Platform Design Guideline, Revision 1.0 is available now – w Design Guideline areas: – Board routing, placement and layout guidelines – EMI/EMC solutions – Front panel USB design guidelines

May 9, Board Design w 4 layer sufficient; trace impedance matching is key w Propagation Delay w Maximum Motherboard Trace Length Of 18 Inches – Cable + Traces 18 Inches For Front Panel Solutions Motherboard Is the Toughest Environment Host Controller Delay (3ns) Cable (26ns) Device (1ns)

May 9, Board Design Guidelines w Board Stack-up: – 4 layer, impedance controlled boards required – Impedance targets must be specified – Ask your board vendor what they can achieve Classic four-layer stack Signal 1 Prepreg VCC Core Ground Prepreg Signal 2 Example target impedance: in trace at 60+/-15% 7.5mil traces with 7.5mil 7.5mil traces with 7.5mil spacing Zdiff 90 spacing Zdiff 90

May 9, 20017May 17, Routing Guidelines w Control trace widths to obtain target impedance – Ask your board vendor what they can achieve – As always, cost is a consideration w Maintain strict trace spacing control w Minimize stubs D-D- D+D+ 15k 15k Correct way to connect to resistors

May 9, Motherboard Front Panel Daughter Card Board Design w Daughtercard at front/side panel – Bypass caps, EMI control components, strain relief w Header and cable – Keyed header, cable of limited length and matched impedance Front/Side Panel Connectors

May 9, 20019May 17, Routing Guidelines w Routing over plane splits w Creating stubs with test points w Violating trace spacing guidelines Common Routing Mistakes Ground or power plane tp Dont cross plane splits Proper routing technique maintains spacing guidelines

May 9, Measurement Techniques w Selecting Appropriate Test Equipment – Accurate measurement of signal quality requires an o-scope and probes with adequate BW and sample rate – Proper test fixtures are also important Equipment that will work Scope: TDS 694C - 10GS/s, 3Ghz Probe: P6247 Fet Probe - 4Ghz,.4pF typ Differential Probe

May 9, w USB 2.0 test mode software will be used to enable device and host controller tests w USB 2.0 test fixture will be used to provide ideal termination for signal quality measurement w Differential signaling requires the use of a differential probe HS Relay Differential Probe Test Mode SW USB 2.0 test fixture HS Device Oscilloscope Board Testing

May 9, EMI w USB1.X EMI solutions dont work for USB2 – Low pass filters damage USB 2.0 HS signal quality D+ D - Vcc USB A Connector Typical USB 1.1 Termination Scheme

May 9, EMI w Common mode chokes are a proven USB 2.0 EMI solution – Refer to the USB 2.0 Design Guideline for solutions that work for USB 2.0 FS & HS signal quality requirements Common Mode Chokes are a Defensive Design!!!

May 9, EMI w Proper grounding of chassis is crucial – Connector shell must connect to green wire ground early and well – IO shield must connect securely to chassis and receptacle w 2 wire common mode choke is preferred – Blocks common mode EMI from leaving chassis – Common mode 100 Mhz should be < 300 Ohms – Differential 100 Mhz should be < 8 Ohms

May 9, ESD, EMC w ESD strikes spread out in time by inductance of cables and hubs in series – Bypass/flyback caps on Vbus near connector help w Hardware Protection – Well-grounded shield – Common mode choke – Spark gap arrestors – Shielded cables

May 9, DP1 DM x s V keyboard glitch ESD, EMC w Differential squelch/disconnect w Pattern matching before connectivity w Sampling over extended times e.g. Chirp w Low speed requires cables with at least a foil shield Noise Immunity Built Into Low-Level Protocol

May 9, USB2 Validation Motherboard Front Panel Test Chip Back Panel Test Chip Test Results

May 9, Routing Paths Tested USB Connector Motherboard PCI SLOT LAN South Bridge NECtest chip chip Long Route Front Panel Header Test Results Motherboard PCI SLOT LAN South Bridge USB Connector Short Route NEC test chip

May 9, TP2 TP3 Validation board Results w Back Panel Eye Pattern Results – EMI/ESD components – Both at A-connector (TP2) and at end of USB cable (TP3) (with ideal termination) – Three-stack connector on MB

May 9, Shielded, twisted pair 18 ribbon cable Early Testing Results w Front Panel Header Cable Options Tested

May 9, Shielded Front Panel Cable Ribbon Front Panel Cable Validation board Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel ribbon cable

May 9, Validation board Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel ribbon cable Connector reference ns exception window Shielded, Twisted Pair Front Panel Cable Ribbon Front Panel Cable Connector reference

May 9, Test Results USB 2.0 host controller Back Panel Front Panel USB 2.0 Motherboard

May 9, USB 2.0 Board Test Results w High Speed Back Panel Eye Pattern Results (Figure 1) w High Speed Front Panel Eye Pattern Results with shielded cable (Figure 2) Figure 1 Figure 2

May 9, Device turns on HS termination Reset USB 2.0 Board Test Results w CHIRP Testing – Measured with single ended probes – At the A-connector (TP2) w Important Parameters – Reset duration – CHIRP K amplitude – CHIRP K duration – HS termination timing – Host CHIRP amplitude

May 9, Summary w USB 2.0 Design Presents New Challenges – Board layout – Common mode chokes – Front Panel Solutions – Signal Quality Measurement – Compliance Testing w USBIF Is Providing Design Guides In Such Areas

May 9, References w USB-IF – w Platform Design guide – w Contact – – –

May 9, Questions?