RTL Design Methodology Lecture 17 RTL Design Methodology SORTING example

Structure of a Typical Digital System Data Inputs Control Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control Outputs

Hardware Design with RTL VHDL Pseudocode Interface Datapath Controller ASM chart Block diagram VHDL code VHDL code

Steps of the Design Process Text description Interface Pseudocode Block diagram of the Datapath Interface divided into Datapath and Controller ASM chart of the Controller RTL VHDL code of the Datapath, Controller, and Top-Level Unit Testbench for the Datapath, Controller, and Top-Level Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing using FPGA board

Steps of the Design Process Introduced in Class Today Text description Interface Pseudocode Block diagram of the Datapath Interface divided into Datapath and Controller ASM chart of the Controller RTL VHDL code of the Datapath, Controller, and Top-level Unit Testbench for the Datapath, Controller, and Top-Level Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing using FPGA board

SORTING example

Sorting - Required Interface Clock Resetn DataIn N DataOut Done RAdd L WrInit S (0=initialization 1=computations) Rd

Sorting - Required Interface

Simulation results for the sort operation (1) Loading memory and starting sorting

Simulation results for the sort operation (2) Completing sorting and reading out memory

Sorting - Example During Sorting 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 After sorting Before sorting i=0 i=0 i=0 i=1 i=1 i=2 j=1 j=2 j=3 j=2 j=3 j=3 Address 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3 1 1 1 1 2 2 3 4 Legend: position of memory indexed by i position of memory indexed by j Mi Mj

Pseudocode [load input data] wait for s=1 [load input data] FOR k = 4 FOR any k ≥ 2 [load input data] wait for s=1 [load input data] wait for s=1 for i = to 2 do for i = to k - 2 do A = Mi ; A = Mi ; for j = i + 1 to 3 do for j = i + 1 to k – 1 do B = Mj ; B = Mj ; if B < A then if B < A then Mi = B ; Mi = B ; Mj = A ; Mj = A ; A = Mi ; A = Mi ; endif ; endif ; endfor; endfor; endfor; endfor; Done wait for s=0 [read output data] go to the beginning Done wait for s=0 [read output data] go to the beginning

Pseudocode wait for s=1 for i=0 to k-2 do A = Mi for j=i+1 to k-1 do B = Mj if A > B then Mi = B Mj = A end if end for Done wait for s=0 go to the beginning

SORTING solutions

Block diagram of the Datapath DataIn RAdd ABMux N L N L Li LD 1 Resetn s Ei EN RST CLK Din s Clock +1 Csel WrInit We DIN WE Lj LD Addr L Resetn Wr i Ej EN RST ADDR CLK Clock CLK Clock 1 DOUT L j L 1 N Mij EA EB = k-2 = k-1 EN CLK RST Resetn EN Resetn RST CLK Clock Clock Rd N N zi zj N 1 Bout A B DataOut A>B Block diagram of the Datapath AgtB

Block diagram of the Datapath DataIn RAdd ABMux N L N L Ei EN 1 Resetn s s Li LD RST CLK Din s Clock WrInit +1 Csel DIN We WE Ej EN Addr L Resetn ADDR i Lj LD RST Wr 1 CLK Clock CLK Clock 1 L DOUT L j 1 N Mij EA EB = k-2 = k-1 EN CLK RST Resetn EN Resetn RST CLK Clock Clock Rd zi N N zj N 1 Bout A B DataOut A>B Block diagram of the Datapath AgtB

Interface with the division into Datapath and Controller RAddr DataIn WrInit Clock Rd Resetn s N L AgtB zi zj Datapath Controller Wr Li Ei Lj Ej EA EB Bout Csel N DataOut Done

ASM Chart of the Controller

Timing justifying the need for the state S3