Day 25: November 8, 2010 Memory Core ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 25: November 8, 2010 Memory Core Penn ESE370 Fall2010 -- DeHon

Today 6T SRAM review 5T SRAM Multiport SRAM DRAM Leakage Charge sharing Precharge Multiport SRAM DRAM Leakage Penn ESE370 Fall2010 -- DeHon

Memory Bank Penn ESE370 Fall2010 -- DeHon

SRAM Memory bit Penn ESE534 Spring2010 -- DeHon

Memory Bank Penn ESE370 Fall2010 -- DeHon

5T SRAM Penn ESE370 Fall2010 -- DeHon

Consider What happens to voltage at A when WL turns from 01 Assume Waccess large Waccess >> Wpu=1 Penn ESE370 Fall2010 -- DeHon

Voltage After enable Word Line QBL = 0 QA = (1V)(g(2+Waccess)C0) CBL>>CA=(g(2+Waccess)C0) After enable Waccess Total charge roughly unchanged Distributed over larger capacitance~=CBL VA=VBL~= CA/CBL Penn ESE370 Fall2010 -- DeHon

Larger Resistance? What happens if Waccess small? Waccess < Wpu Penn ESE370 Fall2010 -- DeHon

Simulation: Waccess=100 Penn ESE370 Fall2010 -- DeHon

Simulation Penn ESE370 Fall2010 -- DeHon

Charge Sharing Charge sharing can pull down voltage Penn ESE370 Fall2010 -- DeHon

Consider What happens to voltage at A when WL turns from 01 Assume Waccess large Penn ESE370 Fall2010 -- DeHon

Simulation Waccess=20 Penn ESE370 Fall2010 -- DeHon

Simulation Waccess=4 Penn ESE370 Fall2010 -- DeHon

Charge Sharing Charge sharing can lead to read upset Charge redistribution adequate to flip state of bit Penn ESE370 Fall2010 -- DeHon

How might we avoid? Penn ESE370 Fall2010 -- DeHon

Precharge to middle Voltage Precharge to Vdd/2 Now charge sharing doesn’t swing to opposite side of midpoint Penn ESE370 Fall2010 -- DeHon

Simulation Waccess=20 Penn ESE370 Fall2010 -- DeHon

Multiport RAM Penn ESE370 Fall2010 -- DeHon

Mulitport Perform multiple operations simultaneously E.g. Processor register file R3R1+R2 Requires two reads and one write Penn ESE370 Fall2010 -- DeHon

Simple Idea Add access transistors Penn ESE370 Fall2010 -- DeHon

Watch? What do we need to be careful about? Penn ESE370 Fall2010 -- DeHon

Isolate BL form Mem Larger, but more robust Essential for large # of read ports Penn ESE370 Fall2010 -- DeHon

Adding Write Port Penn ESE370 Fall2010 -- DeHon

Write Port What options does this raise? Penn ESE370 Fall2010 -- DeHon

Opportunity Asymmetric cell size Separate sizing constraints Weak drive into write port (Wrestore) Strong drive into read port (Wbuf) Penn ESE370 Fall2010 -- DeHon

Multiple Write Ports Penn ESE370 Fall2010 -- DeHon

DRAM Penn ESE370 Fall2010 -- DeHon

1T 1C DRAM Simplest case – Memory is capacitor Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall2010 -- DeHon

1T DRAM What happens when read this cell? Penn ESE370 Fall2010 -- DeHon

1T DRAM On read, charge sharing Small swing on bit line VBL = (Cbit/CBL)Vstore Small swing on bit line Must sense Means want large Cbit Limits bits/bitline so VBL large enough Cell always depleted on read Must be rewritten Penn ESE370 Fall2010 -- DeHon

Dynamic RAM Takes sharing idea one step further Share refresh/restoration logic as well Penn ESE534 Spring2010 -- DeHon

3T DRAM Penn ESE370 Fall2010 -- DeHon

3T DRAM How does this work? Penn ESE370 Fall2010 -- DeHon

3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state Must use Vdd+VTN on BL to write full voltage Penn ESE370 Fall2010 -- DeHon

Some Numbers (memory) Register as stand-alone element  4Kl2 Static RAM cell  1Kl2 SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  100l2 Dynamic RAM cell (SRAM process)  300l2 Penn ESE534 Spring2010 -- DeHon

Energy Penn ESE370 Fall2010 -- DeHon

Single Port Memory What are most cells doing on a cycle? What fraction is involved in a read/write? When not doing a read or write? Reads are slow Cycles long  lots of time to leak Penn ESE370 Fall2010 -- DeHon

ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power Isd,leak 100nA/mm 50pA/mm Isd,sat 1200 mA/mm 560mA/mm Cg,total 1fF/mm 0.91fF/mm Vth 285mV 585mV C0 = 0.045mm × Cg,total Penn ESE370 Fall2010 -- DeHon

High Power V=1V d=1000 g=0.5 Full swing for simplicity Csc = 0 (just for simplicity, typically <Cload) Cload=1000C0 ≈ 45 fF = 45×10-15F WN = 2  Ileak = 9×10-9 A P= (45×10-15) freq + 1000×9×10-9 W Penn ESE370 Fall2010 -- DeHon

Relative Power P= (45×10-15) freq + 1000×9×10-9 W Break even at freq=200MHz Partial swing on bit line Reduce dynamic energy Increase percentage in leakage energy Penn ESE370 Fall2010 -- DeHon

Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process with high Vth Reduce leakage at expense of speed Penn ESE370 Fall2010 -- DeHon

Admin Size your memory cell André office hours Tuesday Andrew office hours Wednesday and Thursday Penn ESE370 Fall2010 -- DeHon

Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall2010 -- DeHon