ATMX150RHA Circuit Design Platform Erwann BERLIVET June 20th 2018

Agenda Introduction Qualified Supply Chain Qualification Process Qualification extension to analog Design Flows Analog IPs Catalog Analog IPs Test results Conclusion

Introduction The ATMX150RHA offer: Is based around a 150nm SOI technology initially developed for Automotive circuit design purpose Was enhanced to achieve Space requirements Is supporting Digital, Analog and Mixed signal circuit development Is a space qualified supply chain

Qualified Supply Chain ATMX150RHA is a space qualified supply chain from technology process to samples delivery Technology Process Design Flow Foundry and probe Assembly and Packaging Final Test Delivery and Traceability

Qualification Process Based on qualification heritage from previous technologies (0.35µm, 0.18µm), internal qualification flow cover ESCC and QML standards requirements for digital circuit design Technology Libraries (timing, physical and behavioral models) Digital On Top Design Flow Standard Evaluation Circuit Foundry, probe and assembly Qualification (characterization, TID, SEE, HTOL, ESD, group D) Quarterly Monitoring (final test, HTOL)

Qualification Extension Domain extension is based on 2 circuits platform: An enhanced SEC embedding representative analog IPs and a monitoring function An Analog Test Vehicle to perform standalone qualification of each analog IP Technology Libraries (timing, physical and behavioral models) Digital On Top Design Flow Enhanced Standard Evaluation Circuit Foundry, probe and assembly Qualification (characterization, TID, SEE, HTOL, ESD, group D) Quarterly Monitoring (final test, HTOL) Libraries (schematic, layout) Analog On Top Design Flow Analog Test Vehicle Qualification (characterization, TID, SEE, HTOL)

Qualification Platforms Standard Evaluation Circuit (169mm², 352pins) Digital (different RAM and logic function, gate count over 11Mgtes equivalent NAND2) Analog (PLL, RC Oscillator, Multiplexer, Linear Voltage Regulator, Bandgap voltage reference) Monitoring cells Analog Test Vehicle (73 mm², 256 pins) Linear Voltage Regulator Bandgap voltage reference Analog multiplexer RC oscillator PLL

Monitoring Function The monitor macro contains different analog functions which performance relies on devices available in the ATMX150RHA PDK: 27 ring oscillators where frequency depends on device type (NMOS/PMOS), oxide type (1.8v/3.3V/5.0V) and geometry (short/long and narrow/wide) 2 bandgap references based on NPN/PNP and 2 types of Rpoly 6 amplifiers with different input stages (NMOS/PMOS) and oxide type (1.8V/3.3V/5.0V) 12 power devices (NMOS/PMOS) with different oxide type (1.8V/3.3V/5.0V/15V/25V/45V)

ATMX150RHA Design Environment Depending on customer requirements and design capacities, different working models are available Physical Design Kit Design Kit Digital Design Analog/Mixed Signal Design OALIB Package Full Custom Design

Design Kit Content Library package for Digital On top Design Flow contains: Timing model Liberty files (nldm, ccs, ccs noise) DB files Physical model LEF Milkyway Redhawk views for IR drop and EM analysis Behavioral model Verilog Vital

OALIB Package Content Library package for Analog On top Design Flow usage contains: IOs and standard cells database: Schematic Layout Analog IPs database: Encrypted netlist (spectre, hspice and eldo) Back annotated Bbox layout

Analog IP Catalog Status IP Name Main Characteristics Maturity TRL3 TRL5 Current Status PLL400MRHA PLL 40-450MHz TRL6 Now Field Release REG200RHA Linear 1.8V 200mA Silicon validation on going (electrical, TID and SEE done) OSCRC10MRHA RC oscillator 4/8/10/12MHz MUX8RHA 8-channel analog multiplexer BG1V2RHA 1.215V Bandgap Reference TRL4 18Q3 Silicon validation on going (electrical and TID done) POR18RHA Power On Reset and voltage monitoring 19Q1 Embedded in SAMRH71 OSCRC32KRHA 32kHz RC oscillator OSCXT32KRHA 32kHz XTAL oscillator OSCXT20MRHA 3-20MHz XTAL oscillator REGD600RHA Fully integrated DCDC 1.8V for digital supply 600mA TRL2 18Q4 19Q4 Under development REGA20RHA Fully integrated Low Noise Linear Voltage Regulator 1.8V 20mA PLLDIVRHA PLL 40-300MHz integrated divider ADC12RHA ADC 12 bits, 1 Msps, ENOB 11 bits 19Q3 DAC12RHA DAC 12 bits, 2 Msps IPs Maturity definition from ECSS-E-HB-11A

Analog IPs Radiation Hardening Hardening by technology Deep trench insertion to isolate NMOS from PMOS to SEL Deep well implants below low voltage area to decrease parasitic thyristor gain to reduce SEL sensitivity while keeping high digital gate density Enclosed Layout Transistor PCells available in the PDK for thick oxide NMOS, including extracted spice model Hardening by design Averaging or filtering on sensitive DC nodes (voltage or current references) Triple Modular Redundancy on critical digital signals Gate splitting and interdigitating of matched devices Avoiding small W/L ratio to reduce TID sensitivity Usage of dummy transistor to collect SEE charge

Analog IP Test Results Voltage Regulator REG200RHA - Linear Voltage Regulator Supply voltage: 3.0V - 5.5V Tj range: -55 to 145°C Output voltage: 1.8V Max Output current: 200mA Voltage reference included Power on reset and Power fail included Hardened by design: Deep trench insertion ELT NMOS Redundancy Averaging Filtering Gate splitting SEE tested up to 65Mev.cm²/mg No SEL event at Vdd=5.5V and TA=125°C No SET event at Vdd=3.0V and TA=25°C TID tested up to 150krad(Si) @300rad/h Output voltage variation in spec, due to NPN sensitivity Radiation Hardness Assurance “R” 100krad(Si)

Analog IP Test Results Bandgap Reference BG1V2RHA 1.215V Bandgap voltage reference Supply voltage: 3.3V +/- 10% Tj range: -55 to 145°C Max Temperature coefficient: 90 ppm/°C Trim less design based on PNP transistors Hardened by design: Deep trench insertion ELT NMOS Averaging Filtering Gate splitting TID tested up to 150krad(Si) @300rad/h Negligible variation observed either on biased or unbiased parts Radiation Hardness Assurance “R” 100krad(Si)

Analog IP Test Results RC Oscillator OSCRC10MRHA Programmable RC oscillator 4/8/10/12 MHz Supply voltage: 1.8V +/- 10% Tj range: -55 to 145°C Frequency accuracy: +/-10% Frequency variation over temp.: +/- 1% Hardened by design: Deep trench insertion Comparator redundancy Reference averaging SEE tested up to 65Mev.cm²/mg No SEL event at Vdd=1.95V and TA=125°C No SET event at Vdd=1.65V and TA=25°C TID tested up to 150krad(Si) @300rad/h No variation observed Radiation Hardness Assurance “R” 100krad(Si)

Conclusion The ATMX150RHA offer : Space qualified supply chain Qualification extension to analog proposed Analog IPs catalog available Silicon results has demonstrated: Design and hardening methodology Technology capability for radhard design