Fixed Latency Serial Links with FPGA-embedded SerDes for SuperB A. Aloisio, R. Giordano In this talk Physics Dept. - University of Napoli “Federico II” and INFN Sezione di Napoli, Italy email: aloisio@na.infn.it, rgiordano@na.infn.it

Outline Fast Links in proposed SuperB DAQ/Trigger architecture Latency issues and FPGA-embedded transceivers A FPGA-based, fixed-latency link latency we developed in Naples Latency tests Future work Conclusion 31/07/2019 Raffaele Giordano

Fast Links in SuperB Trigger/DAQ FCTS: Fast Control and Trigger System FE: Front End ROM: Read Out Module From : D. Breton & U. Marconi proposal for the Electronics Trigger and DAQ architecture of SuperB June 8th 2009. 31/07/2019 Raffaele Giordano

From Previous Meetings and Discussions SuperB FCTS needs clock distribution with constant phase and minimum jitter fixed-latency data transfer On BABAR, that has been achieved with the G-link chip-set. Now obsolete and no equivalent on the market. Off-detector: SerDes embedded in FPGAs should be deployed (the GBT Project at CERN also suggests this approach) On-detector: radiation may prevent deploying FPGAs. Solutions based on radiation-qualified SerDes should be adopted 31/07/2019 Raffaele Giordano

Latency of a Serial Link The latency of a serial link is the delay between data at the input of the link and at the output (from A to B) The phase of the recovered clock (f2) varies with respect to the transmitter clock phase (f1) at each power up of the link 31/07/2019 Raffaele Giordano

Clock phase variation at receiver 31/07/2019 Raffaele Giordano

Latency Variations of a Serial Links Some reasons : FIFOs not always filled with the same number of words before start of reading (leads to n-cycle variation) After clock multiplication and subsequent division the phase information is lost! (leads to m UI variation) E.g. at the receiver, the recovered clock at line rate is divided to obtain the recovered clock for the parallel domain 31/07/2019 Raffaele Giordano

High-Speed FPGA-embedded SerDes Three Vendors: Xilinx, Altera, Lattice, we focus on Xilinx Xilinx Virtex 5 Family includes GTPs transceivers : Up to 3.75 Gb/s 100 mW @ 3 Gb/s Up to 24 in a single FPGA Many customizable features (e.g. word width : 8,10,16 and 20 bits) 8b10b encoding native support They are available as a hard macro or “tile” Picture of V5 FPGA with GTPs 31/07/2019 Raffaele Giordano

GTP Architecture: “Dual” Tile Two Tx/Rx pairs per tile Shared components: PLL, clocking, reset, power, DRP Dedicated clock routing and differential buffer Several clocking schemes can be chosen, depending on input word width, data-rate, latency requirements etc. Package Pins FPGA Fabric 31/07/2019 Raffaele Giordano

A fixed-latency 8b10b link architecture Reference clock @ 62.5 MHz Serializing 10-bit symbols @ 250 MHz => 2.5 Gb/s Also tested @ 56 MHz Fixed data latency and constant clock-phase after reset or power-cycle encoder/decoder external to the GTP 31/07/2019 Raffaele Giordano

Test Bench Two off-the-shelf boards built around a Virtex 5 LX50T FPGA with embedded GTP connected by means of a pair of 5 ns, 50 W coaxial cables Two clock generators for GTP reference clocks Clean reference clock for Tx (sT=4ps), seed clock for Rx (Df < 100 ppm with transmitter clock, sT=15ps) Oscilloscope for latency tests and source analyzer to characterize jitter on the recovered clock 31/07/2019 Raffaele Giordano

Overall Link Latency Tests resetting transmitter and receiver mean = 82.95 ns s = 40 ps 358 ps Tests resetting transmitter and receiver We successfully verified that clock phase and data latency remained fixed during the tests 31/07/2019 Raffaele Giordano

Transmitter and Receiver Latencies 4.5 clock cycles Tx latency: 4.5 parallel clock cycles (@250 MHz 18 ns) 8b10b symbol corresponding to the pulse Rx latency: 15 parallel clock cycles (@250 MHz 60 ns) 15 clock cycles 8b10b symbol corresponding to the pulse 31/07/2019 Raffaele Giordano

Constant clock phase and data latency 31/07/2019 Raffaele Giordano

Clock distribution Our architecture distributes the clock with a constant phase (even after a reset or a power-cycle of the link) This approach allows to distribute the clock on the data network See next talk for jitter analysis of the recovered clock 31/07/2019 Raffaele Giordano

Future Work Select and characterize off-the-shelf Serializers/Deserializers for the on-detector end of the link Fixed-latency data transfer and phase-locked clock distribution in a hybrid link (FPGA-embedded SerDes <-> off-the-shelf SerDes) Test of jitter cleaners Test on GTX, newer Xilinx embedded SerDes (data-rates up to 6.5 Gb/s) 31/07/2019 Raffaele Giordano

Conclusion Successfully implemented and tested an FPGA-based 8b10b link for fast control and trigger applications Recovered clock phase and data latency fixed at each power up of the link (“virtual ribbon cable”) Coding-independent implementation (codec may be changed without losing fixed-latency) Jitter performance of the recovered clock will be presented in the next talk Radiation tolerance for the on-detector end of the link needs to be studied 31/07/2019 Raffaele Giordano