Timing and Event System Status DOE Review of the LCLS Project SC5 - Controls Systems Breakout Session S. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny

Outline Overview – HW Block Diagram and Reqts Progress since February, 2006 Outstanding Issues Task List The Event Definition system - EDEFs

Timing Architecture ~ Linac main drive line ÷4 FIDO ReSychronizer SLC 476 MHz 120 Hz LCLS ÷4 FIDO ReSychronizer 119 MHz 360 Hz SLC MPG P N E T E V G I O C SLC events LCLS events LCLS Digitizer LLRF BPMs Toroids Cameras GADCs Old klystrons I O C E V R Tr ans TTL m P P N E T P D U TTL-NIM convert. SLC Trigs

Hardware Block Diagram Early 2007 Commissioning Modulator Triggers Existing Control System Beam Path Acq and Calibration Triggers BPM FEE PADs and PACs Timing Crate Acc and Standby Triggers E V G F A N 1 F A N 2 P N E T I O C E V R I O C E V R 1 E V R 2 E V R 3 I O C 360Hz Fiducial RF Timing BPM Crates LLRF Crate 119MHz Clock Future MPS Fiber Distribution: Timing Pattern, Timestamp, Event Codes Beam Rate, Beam Path Triggers Triggers Trigger F A N 3 E V R 1 C A M 1 I O C 1 ... E V R 8 C A M 8 I O C 8 F A N 4 E V R 1 C A M 1 C A M 2 I O C 1 … E V R 4 C A M 7 C A M 8 I O C 4 Laser Steering Crate Profile Monitor Crate … …

Event Generator (EVG-200) SLAC PNET Receiver Micro-Research Finland Oy Receives the MPG broadcast sent to SLC micros and passes it to the EVG SFP transceiver Optical signal to EVRs (fan-outs) RF input Event clock divided from RF /1*,/4, ... /12 EVG Fan Out module Line syncronisation input 360 Hz *SLAC addition

Event Receiver – PMC version Event Receiver (EVR-200-RF) Micro-Research Finland Oy Programmable outputs 5(3) TTL level 2 LVPECL level External trigger input SFP transceiver Optical signal from EVG (or fan-out) Recovered RF output Event Receiver – PMC version Event Receiver (EVR-200-RF)

Event System Requirements Event Generator IOC: Send out proper event codes at 360Hz based on: Choose appropriate 60 Hz “Timeslots” compatible with PEP II PNET pattern input (beam code and bits that define beam path and other conditions) Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc. Future – event codes also based on new LCLS MPS and user input Send out system timestamp with encoded pulse ID from PNET Send out event pattern and manage user-defined beam- synchronous acquisition Event Definitions Check for match between user Event Definitions and input PNET pattern at 360Hz and tag matches in outgoing pattern

Other Event System Components MPS Algorithm Processors and Master Pattern Generator (MPG): Rate-liming logic including beam “burst” and “single-shot” modes Send out PNET pattern to EVG and CAMAC controls (for modulator triggers) Klystron standby triggers klystrons operate at fixed rate Triggers move from beam time to standby time Subbooster Interface module (SBI) checks if timing falls within BCS gate

Event System Requirements Event Receiver IOC: Receive event pattern 8.3 msec before corresponding pulse 3 360 Hz pulses ahead Set trigger delays, pulse widths, and enable/disable Set some trigger delays and enable/disables at 120Hz max based on the incoming pattern and local conditions on the IOC e.g. profile monitor IN status Initiate beam-synchronous acquisition based on pattern set by EVG Support beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern User chooses an event code per trigger triggering done in HW when event code received Software triggers Process pre-defined records when specific event codes are received

Tallies for Early 2007 Commissioning 31 EVR modules (mostly PMC) 28 IOCs with EVRs 9 Transition boards 4 EVR Fanouts 120 Hardware Triggers so far All TTL except 2 NIM triggers for QDCs Most require short cables (except LLRF) EVR with RF clock output not yet available All acquisition electronics using either internal clocks, clock output from the RF timing system, or other external clocks

Progress since February, 2006 Hardware problems identified at SLAC: 119MHz clock input In the absence of a ÷1 input, a daughterboard was made containing a clock receiver IC to allow us to input 119MHz directly EVG AC-line input 360Hz fiducial input was rerouted with firmware change to avoid addition of jitter from internal 10 kHz clock and phase shifter Procurement finished Two test stands equipped and available Identified EVR IOCs and triggers needed for March 2007 commissioning Added more HW engineers, software and operations people to the timing team

Status Tasks that have been started: Interface control document Hardware testing – jitter, fanout testing, etc Software testing Beam-synch-acq implementation Cabling plans and documentation Triggering conditions (when to trigger and which event code and delay to use) are pushing more logic from EVG IOC to EVR IO

Still to be done Finish PMC-EVR driver EVG sequence RAM programming at 360Hz EVR logic for trigger attribute change at 120Hz Pulse-to-pulse control of enables, delays, width Event pattern records and timestamp distribution on the EVR IOCs Installation in sector 20 and 21

Timing System Documentation

Hardware Test Stand EVR Output (Trigger Signal) Delay between fid to trigger: Minimum intrinsic system delay + adjustable value EVG Input (360Hz fiducial)

Timing Jitter Test Results Agilent 54845A EVR jitter w.r.t. fiducial PDU jitter w.r.t. fiducial 30 min. 13 ps rms jitter 13 ps rms jitter

Tasks: High-Level Software Beam Synchronous Acquisition Integration with SLC-aware BPM acquisition

Beam Synchronous Acquisition (BSA) EVG Event Definitions (EDEFs) are used for BSA EDEF includes: Beam code SLC PNET bits and LCLS Modifier bits # to average, # to measure Client or System name Permanent System EDEFs are always active 1Hz, 10Hz, Full, Feedback Available to all clients Client applications may reserve a Client EDEF Client receives EDEF # assignment on demand Client proceeds to fill out definition, then sets “GO”

Slots for 20 possible Event Definitions allocated Event Definitions (EDEFs) in the EVG Slots for 20 possible Event Definitions allocated User Defs Fixed Defs

Data structure in the EVR IOC 20 Buffers One for each EDEF 2800 samples per buffer

Synthesizing the EVG Broadcast MPG PNET bits 0x0 0x0 0x0 MPG PNET bits 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 LCLS bits 0x0 0x0 0x3 0x0 Upon match, set “event bit(s)” EDEF EVG to EVR Broadcast 0x0 0x0 0x0 0x0 0x0 inclusion mask 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 exclusion mask 0x0 0x0 0x0 0x0 0x0 EVR IOCs

Low-Level User interface for defining an Event Def

Beam Synchronous Acquisition EVG broadcast at 360Hz checks all active EDEFs against PNET / LCLS Modifier pattern For every pattern to EDEF match, EVG sets appropriate “event bit” EVR IOC BSA device data is fanned out to 20 buffers Identified by its EDEF # or system name Enabled/disabled for acquisition by its “event bit”