3D electronic activities at IN2P3 Most of topics have been addressed during this workshop and at Large consensus on the fact that most promising advances induced by 3D electronic will concern vertex detectors (pixel detectors) and imaging activities Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Pixel’s Vertex detectors : Key-points Spatial resolution  Pixel dimensions Efficiency  In-chip yield + connection’s yield Speed  Pile-up, time-stamping Radiation hardness  SLHC 400 MRad and 10 16 n.eq cm-2 X0 minimum  Material budget Power consumption  Cooling Overall cost All this points should be addressed even if weighting between them will be “collider dependent” Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Hybrid pixel detectors From Orsay team Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Hybrid pixel detectors (Atlas exemple) FE-I3 CMOS 250 nm Done : ATLAS Design Though Dream ? 400 μm 50 μm FE-I4 CMOS 130 nm 250 μm Drastic pixel dimension reduction (cost effective compared to smallest technologies ?) 4 sides buttable structures New mechanical possibilities 50 μm 125 μm 50 μm 100 μm Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

CMOS pixel detectors / from Marc Winter talk Lot of work done in France (Strasbourg) on CMOS detectors Pay attention to : Via filling Increased power budget Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Imaging devices  see Remi Barbier talk Drastic reduction on dead-area zones of hybrid pixel’s Xray-imagers by “simple” wire-bond pad reconstruction on chip back-side (cppm) XPAD3 module Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Join research between IN2P3 labs Aim : “ to define and realize 3 D test structures for technology evaluation” Evaluation of available technologies (IZM, LETI, IMEC, IBM,…) Number of possibilities looks like a nightmare …(but no-way to wait) We need a techno which take into account the overall detector realization “stable” from now to the detector construction Design of a test chip before end of 2008 (techno IBM 0.13µm) Generic evaluation : Daisy chains, yields, resistivities, vias dimensions, vias/ transistors vicinity, SLID, mechanical behavior, radiation hardness More dedicated elements : “Pixel like” analog and digital tiers with links in between        Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Active test chip : some ideas Basic idea is to use IBM 0.13 µm techno and to split the pixel electronic into analog & digital parts: Either by translating the actual FE-I4 prototype design with “minor” changes / (61x14 pixel array- 50*250 µm- submitted in March, overall chip 3x4 mm)  Direct comparison of 2D-3D test results TDAC Amp2 discri Config Logic Preamp FDAC Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Active test chip / some ideas Either by designing a new pixel cell (Conceptual drawing from Orsay) Pixel layer sensor Digital tier Out discri Bump Analogue Amplifier test structures TSV Analogue AOP Pad SLID Pad Sensor layer Digital Tier 50 mm 50 mm Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM

Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM Active test chip.. con’t        Another approach with more « commercial » 3D-suppliers (TEZZARON-in collaboration with FNAL) “Magic” prices ( less than one IBM 0.25µm run) integrated approach Skip partially evaluation phases ? Technology transfer from IBM 0.13 Radiation hardness to be checked May be not completely suitable for CMOS sensors but could be bump-bonded by after on other sensor substrate In all cases testability of separate components and complete system is an issue 4 French labs participating at the moment (Marseille, Orsay, Paris, Strasbourg). Collaboration is needed with others labs (expertise) 200 k€ already obtained and sizeable engineering man-power Ringberg workshop, April 2008 Jean-Claude Clémens, CPPM