Hall D Front End Electronics Fernando J. Barbosa 23 - 24 July 2003 barbosa@jlab.org 7/16/2019

Topics Sensors & Systems Generic Front End Implementation Summary 7/16/2019

Sensors & Systems Drift Chambers 12,000 9,120 2,880 # of Channels ADC TDC Drift Chambers 12,000 9,120 2,880 Central, Forward PMTs & HPMTs 3,405 3,405 1,205 Tagger, Start, Veto Counters Barrel , Forward Calorimeters TOF,Cĕrenkov Semiconductor Silicon -strip Polarimeter 2,048 2,048 VLPC 2,000 2,000 7/16/2019

Generic Front End Driver Rf Copper Fiber Cf CR-(RC)n Semi-Gaussian Shaper Pole-Zero ADC Pipeline To DAQ is Cd BLR Discriminator LE, CFD, ZC Digitization Preamp Preamp parameters chosen for improved S/N, signal rates, power dissipation, etc. On-detector digitization decreases cabling requirements but increases complexity and imposes more stringent requirements on reliability. Copper links should be used in high radiation areas. 7/16/2019

(Wirebonded or Packaged) Implementation Discrete Hybrid & MCM ASIC Semiconductors (SMT) Passives (SMT) FR-4 SMT Caps Semiconductor (SMT) Semiconductor (Wirebonded) Pasted Resistors Ceramic , FR-4, AlN ASIC (Wirebonded or Packaged) Ceramic , FR-4, AlN 7/16/2019

Discrete Component Availability Cheap Proven Technology Reliable Production Control Medium Density 7/16/2019

Hybrid & MCM Component Availability More Expensive Than Discrete Proven Technology Higher Reliability Production Control Medium To High Density 7/16/2019

CP01 – Hybrid ~36K channels installed in Hall B. Recently updated for harsh environments. < $4 per channel. 7/16/2019

ASIC A number of ASICs have been designed for experiments at LHC, FNAL, BNL, etc. … Some of these may fit our requirements … … But may not be available for prototyping or production! … Custom or modified design is a good alternative. Production will depend on technology availability, mask set redesign and cost. Cost justification will depend on the number of chips required. Robust Technology. Highest Reliability. Highest Density. Functional Chip Tests Required!! 7/16/2019

ASDQ ASIC Preamp, Shaper, Discriminator & Q-measurement. 8-channels for Timing and dE/dx - Q is encoded into Output Pulse Width. Designed for CDF ~ 500,000 at FNAL & CERN in several variations. 250 Chips (2000 Channels) per Wafer. Requires mask set Redesign, Production, Packaging & Testing < $15/Channel. Preamp, Shaper & BLR Discriminator & dE/dx + + Input Protect Output Driver - - 7/16/2019

Some ASIC Cost Estimates Prototyping costs depend on Technology** $1K, Qty. 5, 1.50 um AMIS $15K, Qty. 40, 0.25 um TSMC $45K, Qty. 40, 0.13 um IBM Engineering Runs Mask sets may cost ~ $45K Cost per channel ~ $1 *Preliminary results show that deep sub-micron processes at 1.8 um and 1.3 um are radiation tolerant. **Source: MOSIS 7/11/2003 7/16/2019

Support Systems Ancillary Detector PCBs Thermal Constraints Cabling – Routing & Performance Power Supplies & Distribution Grounding Slow Controls … 7/16/2019

Summary … The front end electronics requirements for Hall D are not much different from those in Hall B. Updating the Present Hall B architecture is a viable option but requires preamp, post-amp/discriminators, TDCs, ADCs (?) ... ADB Crates TDC Crates Preamp CP01H Twisted Diff. Pair Shielded & Round Detector To DAQ is Analog dECL Amp & Discriminator 7/16/2019

Summary (cont.) The ASDQ ASIC needs to be redesigned but is a cost effective option for system integration – only additional TDCs are required. … simple and reliable … Other ASICs will become available in the near future (i.e., CARIOCA) and may be cheaper if costs shared with other experiments or institutions. TDC Crates Preamp ASDQ-type Twisted Diff. Pair Shielded & Round To DAQ Detector is LVDS 7/16/2019