Early output logic and Anti-Tokens Charlie Brej APT Group Manchester University 28/08/2019 MAPLD 2004

Overview Synchronous Problems Asynchronous Logic Solutions Why? How? Early Output Anti-Tokens 28/08/2019 MAPLD 2004

Problems: Communication Communication horizon “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997] Clock distributed using wave pipelining 28/08/2019 MAPLD 2004

Problems: Performance Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Cycle time Worst – Average case performance Real Computation 28/08/2019 MAPLD 2004

Clock! What is it good for? No arguing with the clock 9am - 5pm. No excuses! 28/08/2019 MAPLD 2004

Bundled-Data When you finish, do the next task Flexitime Request + Delay Acknowledge When you finish, do the next task Flexitime 28/08/2019 MAPLD 2004

How do you know when you are finished? Synchronous: Estimate Global timing reference Asynchronous (bundled-data) Local delay elements Asynchronous (delay-insensitive) When the data arrives Intrinsic 28/08/2019 MAPLD 2004

Becoming Delay Insensitive Dual-Rail Two wires 00 – NULL 01 – Zero 10 – One (11 – Not used) Four Phase handshake Return to zero R0 R1 Ack 28/08/2019 MAPLD 2004

Early Output Logic Dual-Rail interfaces Output generated as early as possible Two Early output cases If either input is ‘0’ then the output is ‘0’ 28/08/2019 MAPLD 2004

Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to 28/08/2019 MAPLD 2004

Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to 28/08/2019 MAPLD 2004

Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to 28/08/2019 MAPLD 2004

Early Output cases 28/08/2019 MAPLD 2004

Validity Unnecessary late inputs Validity signal Must be acknowledged Must wait until they arrive Validity signal Latch generated Ready to be acknowledged Result before all inputs present Acknowledge after all inputs present 28/08/2019 MAPLD 2004

Synchronisation Hurts No need to wait before generating result Need to wait for input in order to acknowledge it Unnecessary stall 28/08/2019 MAPLD 2004

Anti-Tokens Unnecessary late inputs Proactive approach Stall the entire stage Proactive approach Send a ‘cancel’ signal backward to the source Acknowledge before data arrives Anti-Token latches Assert validity early 28/08/2019 MAPLD 2004

Anti-token generation 1 C 28/08/2019 MAPLD 2004

Anti-token generation 1 A C 28/08/2019 MAPLD 2004

Anti-token Propagation 1 A C 28/08/2019 MAPLD 2004

Anti-token Propagation 1 A A C 28/08/2019 MAPLD 2004

Anti-token Token collisions 1 1 A A 1 1 ? A A 1 ? A 28/08/2019 MAPLD 2004

Anti-token Token collisions 1 1 1 A A 1 1 1 A A 1 1 28/08/2019 MAPLD 2004

Remove Unnecessary computation Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Worst – Average case performance Unnecessary Computation/Delays Real Computation Cycle time 28/08/2019 MAPLD 2004

Summary Asynchronous Delay Insensitive Average case performance Safe No timing assumptions Average case performance Remove unnecessary computation Anti-tokens without mutual exclusion units 28/08/2019 MAPLD 2004