Charles Weems and Tim Richards University of Massachusetts Amherst CoGenT: Automatic Co-Generation of Compilers & Simulators for Dynamically Compiled Languages Eliot Moss, presenter Charles Weems and Tim Richards University of Massachusetts Amherst BARC 1/30/03

Plan of the talk Motivation Generating back-end components Generating simulator components Machine description languages Our approach

Motivation Performance of modern languages Explore hardware features Java as well as C, Fortran Dynamic compilation, GC, exceptions ... Explore hardware features Estimate performance (time, energy, …) Goal: good estimates of performance via simulation

We need a simulator that ... Supports new hardware feature(s) Has accurate performance measures Handles language implementation Dynamic code generation User-mode signal handlers Memory mapping, including SEGV

AND we need a compiler that ... Produces code for the (new) target Does so dynamically Optimizes competently for the target Hard if features very novel Not so bad for ordinary back-end tasks Instruction selection Register allocation Instruction scheduling

Need to automate all of this ... Hard to get simulators right Especially if you want them fast Time-consuming to develop them Can say the same about compilers Point: Generate both, automatically, from machine descriptions

Generating back-ends Prototype framework: Jikes RVM “Baseline” and optimizing compilers Instruction selection Register allocation Instruction scheduling Requires simple timing simulator

Generating back-end components BURS, Cattell, & Instruction selection Jikes RVM (compiler) Framework Machine descriptions Java bytecode semantics baseline compiler Machine Description ISA syntax & semantics Java bytecode semantics baseline compiler object layout LIR semantics BURS rules Machine Description ISA syntax & semantics LIR semantics BURS rules Machine Description ISA syntax & semantics register allocation info Instruction scheduler info simple instruction timing simulator

Generating back-end components Register allocation & Instruction scheduling Jikes RVM (compiler) Framework Machine descriptions baseline compiler object layout Machine Description ISA syntax & semantics object layout Java bytecode semantics BURS rules LIR semantics register allocation info Machine Description ISA syntax & semantics register allocation info Instruction scheduler info simple instruction timing simulator Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Instruction scheduler info simple instruction timing simulator

Generating simulator components Functional simulation Instruction semantics Memory contents/function OS calls Timing simulation Pipelines (instruction, FU timing) Caches, memories, busses, … Mix and match ISAs, pipelines, etc.

Additional simulator components Instrumentation and tracing Easy to adjust Debugging and control

Generating simulator components Functional simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc Machine Description ISA syntax & semantics functional simulator functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

Generating simulator components Timing simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc Machine Description ISA syntax & semantics Target pipeline description timing simulator timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

Machine description languages and their applications SLED [Ramsey and Fernández] λ-RTL [Ramsey and Davidson] Facile [Schnarr] MLRISC [George and Leung] Annotated pipeline graph [Milner] CCL [Bailey and Davidson] We will assemble the best from these

The CoGenT prototype Milner Schnarr Cattell SLED,MLRISC,λ-RTL,etc. Simulator Framework Machine descriptions Jikes RVM (compiler) Framework BURS rules baseline compiler LIR semantics Machine Description ISA syntax & semantics Java bytecode semantics baseline compiler timing simulator functional Machine Description ISA syntax & semantics functional simulator Support components object layout LIR semantics Machine Description ISA syntax & semantics Java bytecode semantics Target pipeline description Java bytecode semantics BURS rules timing simulator Instruction scheduler info simple instruction timing simulator timing simulator Target pipeline description LIR semantics register allocation info Machine Description ISA syntax & semantics debugging support Instruction scheduler info simple instruction timing simulator Target pipeline description