A CCESSING I/O DEVICES

I/O devices accessed through I/O interface. Requirements for I/O interface: –CPU communication –Device communication –Data buffering –Control and timing –Error detection.

CPU Communication: Processor sends commands to the I/O system which are generally the control signals on the control bus. Exchange of data between the processor and the I/O interface over the data bus. Check whether the devices are ready or not.

D ATA B UFFERING : Data transfer rate is too high. Data from processor and memory are sent to an I/O interface, buffered and then sent to the peripheral device at its data rate. Error Detection: I/O interface is responsible for error detection Used to report errors to the processor. Types of errors: – Mechanical, electrical malfunctions, bad disk track, unintentional changes.

Data Register Status/Control Register Address Decoder External Device Interface Logic Data Lines Address Lines Control Lines DataData Status Control I/O INTERFACE B LOCK DIAGRAM

DataRegister:holdsthedatabeing transferred to or from the processor. Status/ControlRegister:contains information relevant to the operation. Dataandstatus/controlregisters:are connected to the data bus. Addressdecoder:enablesthedeviceto recognize its address.

Address DecoderControl Circuits Data & Status Registers Input Device BUS I/O inter fa ce I/O INTERFACE FOR I NPUT D EVICE Address Lines Data Lines Control lines

I/O INTERFACE FOR O UTPUT D EVICE Address DecoderControl Circuits Data & Status Registers Output Device BUS I/O interface Address Lines Data Lines Control lines

I/O INTERFACE T ECHNIQUES

10 I/O P ORTS  4 registers - status, control, data-in, data-out – Status-stateswhetherthecurrent commandis completed, byte is available, device has an error, etc – Control-hostdeterminestostarta commandor change the mode of a device – Data-in - host reads to get input – Data-out - host writes to send output  Size of registers - 1 to 4 bytes

I/O devices can be interfaced to a computer system I/O in 2 ways: Memory Mapped I/O I/O mapped I/O

12 M EMORY -M APPED I/O (1) Memory Address Space I/O Address Space (a)Separate I/O and memory space (b)Memory-mapped I/O (c)Hybrid

M EMORY M APPED I/O No need of special I/O instructions. Memory related instructions are used for I/O related operations.

I/O M APPED I/O Memory Address Space I/O address Space Total Address Space

I/O M APPED I/O If we want to reduce the memory address space, we allot a different I/O address space, apart from total memory space.  Memory related instructions do not work here  Processor use these mode only for I/O Read, I/O Write.

D IFFERENCE BETWEEN M EMORY M APPED I/O & I/O MAPPED I/O Memory Mapped I/OI/O Mapped I/O Memory & I/O share the entire address range of processor Processor provides separate address range for memory & I/O Processor provides more address lines for accessing memory Less address lines for accessing I/O More Decoding is requiredLess decoding is required Memory control signals used to control Read & Write I/O operations I/O control signals are used to control Read & Write I/O operations

P ROGRAMMED I/O

I/O operation means –A data transfer between an I/O device & memory or –Between I/O device & Processor. If any I/O operations are completely controlled by processor, then the system is said to be using “ Programmed I/O” –ProcessorhastocheckI/Osystemperiodically until the operation completes  “POLLING” –Microprocessor has to check if any device need service.

P ROGRAMMED I/O Address Decoder & & & Int A? Int C? Int Z? Service routine Z Service routine C Service routine A j j j

Priority:  The Routines assigns priority to the different I/O devices  Port A is always checked 1 st.  Then Port B  Then Port C  Order may change by changing routine.

When Programmed I/O techniques is used: –Processor fetches I/O related instructions from memory and Issues I/O commands to I/O system to execute the instruction. –Memory Mapped I/O & I/O mapped I/O technique may apply. –Processor has 2 separate instructions IN & OUT for data transfer. –When the I/O instruction is encountered by the processor the I/O port is expected to be ready to response. Processor is usually programmed to test the I/O device status before initiating a data transfer.