Circuit Simplification and Karnaugh Map

Example Obtain the truth table of the following function and express the function in some of minterms and product of maxterms F = (xy + z) (y + xz) F = xy + xyz + zy + xz (By distributive law) F = x’yz + xy’z + xyz’ + xyz (By looking at 1’s in F columns of the table) = S (m3, m5, m6, m7) F’ = x’y’z’ + x’y’z + x’yz’ + xy’z’ (By looking at the 0’s in F column of the table) (F’)’ = (x’y’z’ + x’y’z + x’yz’ + xy’z’)’ = F F = (x+y+z) ( x+y+z’) (x+y’+z)(x’+y+z) = P (m0, m1, m2, m4) xyz F 000 001 010 011 1 100 101 110 111

Why it is important to convert functions to SoP and PoS ? Suppose we have the following function F = AB + C(D + E) This function is non-standard. The digital circuit implementation of this function is This implementation requires an AND gate (A . B) and an OR gate (D + E) that makes the first level of circuit. The second level of circuit would be OR gate that gets the input from the first level OR gate and input C The third level is another OR gate that accepts the result of first and second level gates as input and produce F as output result B A C D E

F = AB + C (D+E) = AB + CD + CE Now the function F can be changed to standard form by using the distributive law to remove the parenthesis F = AB + C (D+E) = AB + CD + CE The SoP expression can be implemented as follows: A B F = AB + CD + CE C D C E

The implementation of SoP expression needs only two levels of circuit design. First level is 3 AND gates that accepts the input A, B, C, D, E. The second level is an OR gate that accepts the result of the first level gate as input and produce function F as output A two level implementation of a circuit is faster In general, a two level implementation is preferred because it produces the least amount of delay through the gates when the signal propagate from the inputs to the output The delay that occur for the signal to pass through the gates is called Propagation Delay.

Other Logic Operations and Logic Gates x y F 0 0 0 0 1 0 1 0 0 1 1 1 y x F= xy AND x y F 0 0 0 0 1 1 1 0 1 1 1 1 y x F= x+y OR x F 0 1 1 0 F= x’ Inverter x x F 0 0 1 1 F= x Buffer x x y F 0 0 1 0 1 1 1 0 1 1 1 0 y x F= (xy)’ NAND x y F 0 0 1 0 1 0 1 0 0 1 1 0 y x F= (x+y)’ NOR x y F 0 0 0 1 0 1 0 1 1 1 1 0 Exclusive or (XOR) y x F= x + y x y F 0 0 1 1 0 0 0 1 0 1 1 1 y x F= (x + y)’ = xy + x’y’ Exclusive NOR

The AND, OR and Inverter gates were defined before The Inverter gate inverts the logic value of a binary variable It produces the NOT (complement) function The small circle in the output of the graphic symbol of an inverter (referred to as bubble) designates the logic complement The triangle symbol by itself designates a buffer gate A buffer produces the transfer function but does not produce a logic operation since the binary value of output is equal to the binary value of the input

The NAND function is the complement of the AND function as indicated by graphic symbol that consists of an AND graphic symbol followed by a bubble (symbol of inverter ) The NOR function is the complement of the OR function as indicated by graphic symbol that consists of an OR graphic symbol followed by a bubble (symbol of inverter) The NAND and NOR gates are extensively used as standard logic gates and are in fact far more popular than the AND and OR gates This is because NAND and NOR gates are easier and cheaper to make (compare to AND or OR gates) and digital circuits can be easily implemented with them The exclusive or (XOR) gate has a graphic symbol similar to OR gate except for addition curved line on the input site. Exclusive NOR gate (XNOR) is complement of XOR, as indicated by small circle on the output side of the graphic symbol

Optimization of Logic Functions As was stated earlier, all logic functions can be expressed in canonical form directly from a truth table. However, implementing directly from the canonical form doesn’t necessarily yield the most efficient circuit. Simplification via algebraic manipulation is not always obvious or practical for functions with a large number of variables. Though a truth table is a unique representation for a function, the algebraic and physical implementations are non-unique. As a result, we want to determine which implementation will yield an optimal circuit. The complexity of a digital circuit that implements a Boolean function is directly related to the complexity of its algebraic expression. Thus we want to be able to generate the simplest algebraic expression possible.

Karnaugh Map The map method provides a straightforward procedure for simplifying Boolean functions. It was first proposed by E.W. Veitch (1952) and modified by M. Karnaugh (1953), and as a result, is known as a "Veitch diagram" or "Karnaugh map". The map method is a graphical technique for functional simplification. It is a transformation of a truth table into a diagram made up of cells with each cell representing one minterm. The map method is based upon the combining property, and arranges the minterms such that it becomes obvious which minterms can be combined. Since, any Boolean function can be represented as a sum of minterms, a Boolean function can be represented in the map by those cells which match the minterms included in the function.

Two, and Three Variable Maps As there are four minterms for two variables, the two-variable map contains four cells, one for each minterm. If we wish to represent the function f=xy on a Karnaugh map, we need to remember xy is equal to m3 and is represented in the map by placing a "1" inside the cell that represents m3. xy xy’ x’y x’y’ 1 y x x y m3 m2 m1 m0 y 1 y x x

Example Represent the function f=x+y on a Karnaugh map A three-variable map contains eight cells for the three binary variables. It is important to note that the minterms are not arranged in order, but in a sequence that only one variable changes between adjacent cells. y x 1 1 1 1 1 y yz x 00 01 11 10 m0 m1 m3 m2 m4 m5 m7 m6 x’y’z’ x’y’z x’yz x’yz’ xy’z’ xy’z xyz xyz’ x 1 z

Minimization with Maps Due to the arrangement of cells within the Karnaugh map, any two adjacent cells differ by only one variable. From the Boolean algebra law, it follows that the sum of two minterms in adjacent square can be simplified to a single AND term consisting of only two literals To clarify this, consider the sum of two adjacent square such as m5 and m7 f= S(m5,m7): m5 + m7 = xy’z + xyz = xz (y’+y) = xz Here the two squares differ by the variable y which can be removed when the sum of the two minterms is formed. Thus any two minterms in adjacent squares that are ORed together will cause a removal of a different variable Next example explains the procedure for minimizing a boolean function with a map

Example Simplify the Boolean function F (x,y,z) = S (m2, m3, m4, m5) First, 1 is marked in each midterm that represents the function The squares for minterms 010, 011, 100, and 101 are marked with 1’s. The next step is to find the possible adjacent squares. These are indicated in the map by two blue rectangles, each enclosing two 1’s The upper right rectangle represents the area enclosed by x’y This is determined by observing that the two square area in the row 0 corresponding to x’ and the last two columns corresponding to y y yz x 00 01 11 10 1 x 1 z

Example Continue ….. Similarly, the lower left rectangle represents the product term xy’ (the second row represents x and two left columns represents y’) The logical sum of these two product terms gives the simplified expression F = x’y + xy’

Example Simplify the Boolean function F (x,y,z) = S (m3, m4, m6, m7) There are 4 squares marked with 1’s, 1 for each minterm of the function. Two adjacent squares are combined in the third column to give a 2 literal term yz. The remaining two squares with 1’s are also adjacent by the new definition and are shown in the diagram with their values enclosed in half rectangles These two squares when combined give the two literal term xz’. The simplified function become F= yz + xz’ y yz x 00 01 11 10 1 x 1 z

Consider now any combination of four adjacent square in three variable map Any such combination represents the logical sum of four minterms and results in a expression of only one literal As an example, the logical sum four adjacent minterms m0, m2, m4, m6 reduces to a single literal term z’ m0 + m2 + m4 + m6 = x’y’z’ + x’yz’ + xy’z’ + xyz’ = x’z’(y’+y) + xz’(y’+y) = x’z’ + xz’ = z’(x’+x) = z’ The number of adjacent square that may be combined must be always represent a number that is a power of 2 such as 1, 2, 4, and 8

As a larger number of adjacent squares combined, we obtain a product term with fewer literal One square represents one minterm given a term of three literals Two adjacent squares represents a term of two literals Four adjacent squares represents a term of one literal Eight adjacent squares takes the entire map and produce the function that always equal to 1