Power-Aware DVFS on PowerPC 405LP: Front Bus Scaling Mohamed Nishar Kamaruddin Santhosh Selvaraj OVERVIEW Previous work with the IBM 405LP board showed that Feedback-DVS of the processor voltage and frequency produces considerable power savings. Our work is to study the frequency scaling for the memory subsystem to achieve power savings. We also study the feasibility of integrating this with the existing feedback DVS-EDF scheduling schemes.

Development up to present Experimented with different operating points including those with same processor frequency but with different memory subsystem frequencies. Changes to data acquisition programs and sample applications to record the power savings of the memory subsystem. Integration of PLB frequency scaling into the existing feedback DVS-EDF scheduling schemes.

Results Frequency scaling of the memory subsystem was found to produce significant power savings. Reducing the FSB freq from 100MHz to 50 MHz for a tight noop looped application produced nearly 34% energy savings. Fitting this into the PID Feedback scheduling - we changed all operating points to use half of their original PLB frequencies. Energy savings now: 1.38%. This is because the various operating points defined in the PID feedback scheduling code already scale PLB frequency along with processor frequency. For memory intensive operation, energy savings: 1.1%