Bus Serialization for Reducing Power Consumption Naoya Hatta†, Niko Demus Barli††,Chitaka Iwama†, Luong Dinh Hung†,Daisuke Tashiro†, Shuichi Sakai†, Hidehiko Tanaka††† † University of Tokyo †† Texas Instruments Japan ††† Institute of Information Security

Introduction Wiring power consumption is an important issue on VLSI design SoC and Chip Multiprocessor require buses with long wires Bus serialization for reducing bus power consumption

Outline Proposition Evaluations Conclusion Future Works Objective Bus Serialization Layout Optimization Evaluations Conclusion Future Works

Proposition

Objective T = M f P = a T C V2 Throughput must not decrease We want to T: Throughput M: The number of wires f: Bus frequency P = a T C V2 We want to reduce Power P: Power a: Activity C: Bus capacitance V: Voltage swing

Bus Serialization Reduce bus capacitance Low power and high frequency - by decreasing the number of wires Serializer Deserializer Wire Serialized Bus Latch Wire Conventional Bus Low power and high frequency

Layout Changes The number of wires (M) decreases Pitch Pitch The number of wires (M) decreases Wire resistance (R) decreases Wire capacitance (C) decreases Without increasing area

Parameters Change T = M f f ∝ 1 / R C P = a T C V2 ? M decreases Require higher f - for remaining T Meet the requirement Objective ? R, C decrease f ∝ 1 / R C f increases P = a T C V2 C decreases Power decreases

Layout Optimization T > 100 % Minimum C (=Minimum P) Best width

Why power decreases? P = f C V2 P = M f C V2 C  C / 2 f  2 f P = f C V2 Power doesn’t decrease? C  C / 2 f  2 f P = M f C V2 Power decreases! M  M / 2

Evaluation

Condition Bus Specification Wire Configurations (width, height, etc…) Bus width: 64bit The number of wires (conventional): 64 The number of wires (serialized): 32 Wire Configurations (width, height, etc…) From International Technology Roadmap for Semiconductor 2002 Bit pattern Address bus and data bus between L1 cache and L2 cache L1 cache (data/inst) :16KB, 2way, 64byte block SPECint95 benchmark Compare to conventional (fully parallel) bus

Bus Capacitance The effect of serialization increases as gate length shrinks

Bus Power Consumption Power decreases by 34%

Why Power Increases? Power is consumed Extra Transition Conventional Bus 1 The number of transitions increases by serialization When the same bit pattern is transferred every cycle, extra transition occurs. In address bus, this situation frequently appears. Power is consumed Extra Transition Serialized Bus 1

Differential Data Transfer (DDT) Bit Pattern Normal DDT 0010011010 0010011011 0010011100 0010011010 0010011011 0010011100 0010011010 0000000001 0000000111 Extra Transition occurs Extra Transition doesn’t occur Transfer the difference between present data and previous data

Bus Power Consumption (DDT) Power decreases by 27%

Comparison DDT is useful in Address. In Data, not useful In 45 nm technology, power decreases by about 30%

Power of Peripheral Circuits The additional power of peripheral circuits is 2% of the power consumed by wire 180nm process Wire length: 5mm

Conclusion Normal serialized bus is proper to data bus Serialized bus with DDT is proper to address bus Bus serialization technique decreases power consumption by 30% of conventional in 45nm process As gate length shrinks, Bus serialization becomes more effective

Future Works Apply to Chip Multiprocessor Additional costs of DDT Between L1 cache and L2 cache Additional costs of DDT Additional circuits and delay

Capacitance Model

Power increasing by DDT 10 00 10 1

Bus Power Model

Additional Delay Conventional bus: 0.17ns Serialized bus: 0.15ns