Circuit Switch Design Principles IEG4020 Telecommunication Switching and Network Systems Chapter 2 Circuit Switch Design Principles

Fig. 2.1. An N x N switch used to interconnect N inputs and N outputs Space-Domain Circuit Switching 1 2 N . Inputs Outputs Fig. 2.1. An N x N switch used to interconnect N inputs and N outputs

Fig. 2.2. Bar and cross states of 2 x 2 switching elements Strictly Nonblocking Bar State Cross State Fig. 2.2. Bar and cross states of 2 x 2 switching elements

Fig. 2.3. (a) Crossbar switch Strictly Nonblocking 1 2 3 4 Inputs Outputs Connections: Input 1 to Output 3 Input 2 to Output 4 Fig. 2.3. (a) Crossbar switch

Blocking 1 2 3 4 Blocking: Input 2 cannot be connected to output 2 if input 1 is already connected to output 1 1 2 3 4 Fig. 2.3. (b) banyan switch

Nonblocking Properties RNB WSNB SNB RNB — Rearrangeably Nonblocking WSNB — Wide-sense Nonblocking SNB — Strictly Nonblocking

Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking switch 1 2 3 4 Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking switch

Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked Rearrangements 1 2 3 4 Connection cannot be set up between input 4 and output 1 Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked 1 2 3 4 Connection can now be set up between input 4 and output 1 Fig. 2.4. (c) Same connection request can be satisfied by rearranging the existing connection from input 2 to output 2

Two states corresponding to the same mapping : 1 2 3 4

Complexity of nonblocking switches : How to build large switch from smaller switches? Problems with two-stage networks : 1 2 m . (a) N = mn # lines = m2n = mN Bandwidth expansion factor = m (b) n

Fig. 2.5. (a) An example of one-to-one mapping from input to output 1． 2． 3． 4． ．1 ．2 ．3 ．4 Fig. 2.5. (a) An example of one-to-one mapping from input to output

Fig. 2.5. (b) Number of crosspoints needed for nonblocking switch N! mappings M crosspoints 1 2 N . Fig. 2.5. (b) Number of crosspoints needed for nonblocking switch

Fig. 2.6. A three-stage clos switch architecture Clos Switching Network n1 × r2 r1 × r3 r2 × n3 . (1) (2) (r1) (r2) (r3) n1r1 = n3r3 = N for N × N switch ri — # switch modules in column i n1 — # inputs in column 1 module n3 — # outputs in column 3 Necessary condition for nonblocking: Fig. 2.6. A three-stage clos switch architecture

Fig. 2.7. An example of blocking in a three-stage switch Key: Find a commonly accessible middle node from both input and output nodes A F G B 1 2 3 4 5 6 7 8 9 H A request for connection from input 9 to output 4 is blocked SA = middle-stage nodes used by A = { F, G } SB = middle-stage nodes used by B = { H } Fig. 2.7. An example of blocking in a three-stage switch

Fig. 2.8. The connection matrix of the three-stage network B F G H F,G,H 2 1 A r1 B r2 Stage 1 switch Stage 3 switch Fig. 2.8. The connection matrix of the three-stage network

Fundamental Conditions Conditions of a Legitimate connection Matrix :

Condition for Strictly Nonblocking

Condition for Rearrangeably Nonblocking Rearrangement —— Substituting symbols in connection matrix such that 1.) Matrix remains legitimate 2.) An unused symbol in row A and column B can be found

Condition for Rearrangeably Nonblocking SB ‧D SA ．C

. . A’ A B’ B A’’ A’” B” Connection between A and B is blocked Chain terminates at A” because Fig. 2.9. (a) A chain of C and D originating from B . A’ A” A A”’ . B’ B B” C D A already connected to all middle-stage nodes except D B already connected to all middle-stage nodes except C Only links used by connections in the chain are shown Fig. 2.9. (b) Physical connections corresponding to the chain

There should be two end points in a chain A loop in the chain D occurs twice in this column, making the matrix illegitimate (i.e. physically impossible in associated switch) There should be two end points in a chain Fig. 2.10. Illustration showing loops in chains are not permitted in legitimate connection matrix

D can now be put in entry (A, B) Fig. 2.11. (a) Rearrangement of the chain in Fig. 2.9. . . . A’ . B’ C . A” . . B . A . D . B” . A”’ . Fig. 2.11. (b) Corresponding rearrangement of connections

. . Fig. 2.12. (a) Two chains, one originates from B, one from A D C . A B Fig. 2.12. (a) Two chains, one originates from B, one from A D C . A B This column search ends in C, which is not possible Start searching from B. Column search always looks for D Fig. 2.12. (b) Illustration that the two chains cannot be connected

How many rearrangements? A new row/column is covered each time a point is included (r1 + r3 – 2) other rows and columns At most (r1 + r3 – 1) rearrangements (loose) Basic: consider two chains, one originates from row A, one from column B Choose the shorter chain for rearrangement A composite move: a move in chain 1 with a move in chain 2 At most r1 – 2 moves before all rows exhausted At most r3 – 2 moves before all columns exhausted

Benes Switching Network 2 x 2 . 1 2 3 4 N-1 N Fig. 2.13. Recursive decomposition of a rearrangeably nonblocking network

Benes Network - Complexity Number of 2x2 elements in Benes Network :

Benes Network - Structure 1 2 3 4 5 6 7 8 Baseline Network Reverse Baseline Network Fig. 2.14. An 8x8 Benes Network

Baseline and Reverse Baseline Networks

Fig. 2.15. Illustration of a looping connection setup algorithm Looping Algorithm 1 2 3 4 5 6 7 8 Set up paths for input-output pairs : (1, 4), (2, 5), (3, 6), (4, 3) (5, 7), (6, 8), (7, 1), (8, 2) Central Algorithm: # steps = N logN Fig. 2.15. Illustration of a looping connection setup algorithm

Properties of Benes Network 1.) Unique path property of underlying baseline and reverse baseline networks 2.) Binary tree to middle-stage nodes An input can reach 2j-1 nodes at stage j, j <= log2N 3.) Reachability of nodes in baseline/reverse baseline networks: A node in stage i can be reached by 2i inputs and can reach 2n-j+1 outputs 4.) Middles nodes blocked by an existing path

Cantor Network . 1 2 N m = 1 m = log N Fig. 2.16. Cantor network

Cantor Network – Strictly Nonblocking Cantor Network is SNB : 1.) Let m be # of Benes Network required 2.) Worst case: all other N-1 inputs/outputs busy → there are (N-1) paths to middle nodes 3.) One path meets the binary tree at stage 1 Two paths at stage 2 An example of 8 x8 Benes network Stage 1 Stage 2 …

Cantor Network – Strictly Nonblocking 4.) A node in stage i blocks 5.)

1 2 3 4 5 6 7 8 Connection paths from inputs 1 and 2 intersect with binary tree from the first time in stage 2 If input 4 is connected to this link: a subtree is formed by the three subsequent nodes Therefore the two lower middle-stage nodes are eliminated from connection by input 3 Fig. 2.17. Binary tree extended from an input to all middle-stage nodes

# middle nodes blocked from inputs .

Time-Domain Switching U X Space division switch Fig. 2.18. Performing time-slot interchange using space-division switch

Time-Domain Switching TSI Write Read a b c RAM Switching in time domain Write Address Sequence = a, b, c Read Address Sequence = b, a, c Fig. 2.19. Direct time slot interchange using random access memory (switching in the time domain)

Example for Time-Domain Switching

Fig. 2.20. A time-space-time switch Time-Space-Time Switching TSI r x r . n m n, m : number of time slots per frame at various points Fig. 2.20. A time-space-time switch

Fig. 2.25 A time-space time switch Time-Space-Time Switching ( i, j ) — data on input i at time-slot j C(1,3) B(1,2) A(1,1) F(2,3) E(2,2) D(2,1) L(3,3) H(3,2) G(3,1) 3 x 3 TSI 1 3 2 Frame Targeted Outputs Fig. 2.25 A time-space time switch

Time-Space-Time Switching D(2,1) M U X TSI (1) (2) (3) CBA BAC EDC CED B(1,2) E(2,2) C(1,3) C(1,3) D(2,1) A(1,1) FED EDF HAL LHA E(2,2) H(3,2) F(2,3) L(3,3) G(3,1) G(3,1) LHG HGL BGF GBF H(3,2) B(1,2) L(3,3) F(2,3) Fig. 2.21. Equivalent of time-space-time switching and three-stage space switching

3 x 3 C(1,3) B(1,2) A(1,1) F(2,3) E(2,2) D(2,1) L(3,3) H(3,2) G(3,1) ( i, j ) — data on input i at time slot j Time Slot 1 Time Slot 2 Time Slot 3 Fig. 2.21. Input-output mapping changes from slot to slot in space-division switch in time-space-time switching

These lines correspond to time slot 1 A(1,1) B(1,2) F(2,3) E(2,2) L(3,3) H(3,2) G(3,1) (1) (2) (3) Module (i) corresponds to time slot i of space-division switch in time-space-time switch Module (i) corresponds to input TSI (i) in time-space-time switch Module (i) corresponds to output TSI (i) in time-space-time switch Fig. 2.22. Equivalent of time-space-time switching and three-stage space switching ~END~