DC and RF Modeling of CMOS Schottky Diodes Wenyuan Zhang, Yang Tang and Yan Wang Tsinghua University June 21st 2019 Good afternoon! I’m very glad to stand here and give this presentation, in which I will introduce to you a novel DC and RF model of CMOS Schottky diodes.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion First, I’d like to talk about the motivation.

Motivation CMOS Schottky diodes They have attracted great interests in the field of mm-wave and THz detecting and imaging [1]. A number of researches have been conducted on their structures [2], [3], characterization [4] and circuit applications [5], [6]. In recent years, Si Schottky diodes have attracted great interests in the field of millimeter-wave and terahertz detecting and imaging, and a number of researches have been conducted on their structures, their characterization and their applications in circuits. [1] W. Zhang and Y. Wang, International Applied Computational Electromagnetics Society Symposium, p. 1-2 (2017). [2] S. Sankaran and K. K. O, IEEE Electron Device Letters, v. 26, n. 7, p. 492-494 (2005). [3] S. Sankaran et al., IEEE International Solid-State Circuits Conference, p. 202-203, 203a (2009). [4] M. K. Matters-Kammerer et al., IEEE Transactions on Electron Devices, v. 57, n. 5, p. 1063-1068 (2010). [5] E. Seok et al., Symposium on VLSI Circuits, p. 142-143 (2006). [6] R. Han et al., IEEE Journal of Solid-State Circuits, v. 48, n. 10, p. 2296-2308 (2013).

Motivation CMOS Schottky diodes: structures Structure Shallow Trench Separation (STS) [2] Polysilicon Gate Separation (PGS) [3] Structure diagram Technology 130nm CMOS Series resistance 13Ω 8Ω Junction capacitance 8fF 10fF Cut-off frequency 1.5THz 2THz Let’s look at some typical examples. A CMOS Schottky diode structure of shallow trench separation was proposed in 2005, and it achieved a cut-off frequency of 1.5THz. In 2009, another structure of polysilicon gate separation was reported, and the cut-off frequency was improved to 2THz. [2] S. Sankaran and K. K. O, IEEE Electron Device Letters, v. 26, n. 7, p. 492-494 (2005). [3] S. Sankaran et al., IEEE International Solid-State Circuits Conference, p. 202-203, 203a (2009).

Motivation CMOS Schottky diodes: applications in imaging systems Circuit Structure Device Structure Tech. Array Freq. GHz RV kV/W NEP pW/Hz1/2 Year Ref. (a) STS SBD 130nm CMOS / 180 2006 [5] (b) PGS SBD 2×2 280 0.25 33 2011 [7] (c) 4×4 0.336 24 2013 [6] (d) 860 0.273 42 These progresses made CMOS Schottky diodes suitable for terahertz imaging systems. In 2006, a shallow-trench-separated Schottky diode was used to demonstrate a 180GHz detector, but the performance indicators were not given. A 280 GHz detector using a polysilicon-gate-separated Schottky diode was reported in 2011, and a two-mode imaging array was further realized in two years. The detection frequency was also successfully increased to 860 GHz in 2013. These imaging systems achieved excellent performances, despite high operation frequencies. [5] E. Seok et al., Symposium on VLSI Circuits, p. 142-143 (2006). [6] R. Han et al., IEEE Journal of Solid-State Circuits, v. 48, n. 10, p. 2296-2308 (2013). [7] R. Han et al., IEEE Journal of Solid-State Circuits, v. 46, n. 11, p. 2602-2612 (2011).

Motivation CMOS Schottky diodes They have attracted great interests in the field of millimeter-wave and terahertz detecting and imaging [1]. A number of researches have been conducted on their structures [2], [3], characterization [4] and circuit applications [5], [6]. Their modeling is far below expectations and severely limits the development of their circuit applications. However, few studies are carried out on DC and RF modeling of Si Schottky diodes. Compared to fledged transistor models, Schottky diode modeling is far below expectations and severely limits the development of its circuit applications. Therefore, a compact Si Schottky diode model that can be used in CAD tools is crucially needed, and we are to propose a complete DC and RF model. [1] W. Zhang and Y. Wang, International Applied Computational Electromagnetics Society Symposium, p. 1-2 (2017). [2] S. Sankaran and K. K. O, IEEE Electron Device Letters, v. 26, n. 7, p. 492-494 (2005). [3] S. Sankaran et al., IEEE International Solid-State Circuits Conference, p. 202-203, 203a (2009). [4] M. K. Matters-Kammerer et al., IEEE Transactions on Electron Devices, v. 57, n. 5, p. 1063-1068 (2010). [5] E. Seok et al., Symposium on VLSI Circuits, p. 142-143 (2006). [6] R. Han et al., IEEE Journal of Solid-State Circuits, v. 48, n. 10, p. 2296-2308 (2013).

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion

Model Description DC model Thermionic emission Carrier velocity saturation Tunneling Complete model Vj Vs V The equivalent circuit model, which consists of DC and RF parts, is given in Fig. 1. All the model components have explicit physical meanings. As for DC parts, the basic thermionic emission current is expressed by Schottky equation along with the series resistance Rs in (1), and the corresponding R-V relations are derived in (2) and (3). An increase of the differential resistance at large forward bias is observed. It is mainly because the carrier mobility decreases in large electric field, and it is modeled by making Rs no longer constant but bias-dependent, which is expressed in (4). Leakage current generated from tunneling effect exists at reverse bias, and it is modeled by the tunneling resistance Rt in parallel, which is expressed in (5). So far, the complete I-V relations are equivalent to the R-V relations given in (6).

Model Description RF model Junction capacitance Cj Barrier capacitance Diffusion capacitance Stray capacitance Cp and stray resistance Rp Coupling influences between electrodes Stray inductance Ls Parasitic interconnect influences As for RF parts, the junction capacitance consists of the barrier capacitance and the diffusion capacitance. The barrier capacitance is expressed in (7), and it is dominating at reverse bias. At forward bias, minority carriers inject into Si, generating the diffusion capacitance, and it is usually larger than the barrier capacitance. Besides, the stray capacitance Cp and the stray resistance Rp take all the coupling influences between the diode electrodes into account, while the stray inductance Ls describes all the parasitic interconnect influences.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion To help use the model in CAD tools, a complete step-by-step parameter extraction flow is developed as follows.

Parameter Extraction DC extraction 1. Extract Is and n at small forward bias 2. Extract Rs0, Im, Vm and nm at large forward bias 3. Extract It and nt at reverse bias Is and n are extracted at small forward bias, where Rs and Rt can be neglected. They are calculated from the slope and intercept of the linear regression in (8). Rs0, Im, Vm and nm are extracted at large forward bias, where Rt can be neglected. Rs0 is calculated to be the minimum value of Rs in (9), and Im, Vm and nm are then calculated from the linear regression in (10). It and nt are extracted at reverse bias, where Rj and Rs can be neglected, for Rt is much larger than Rs. They are calculated from the linear regression in (11). So far, all the DC parameters are obtained.

Parameter Extraction RF extraction 4. Extract Ls at small forward bias at high frequency 5. Extract Nd, Vbi and Cp at reverse bias at low frequency 6. Extract Rp at reverse bias at high frequency Ls is extracted at mall forward bias at high frequency, where these approximations in (13) hold true. The diode impedance and its imaginary part are given in (12) and (13), and Ls is calculated from (13). Nd, Vbi and Cp are extracted at reverse bias at low frequency. The admittance of the diode excluding Ls and its imaginary part are given in (14) and (15). Cp is set to be zero as an initial value, so Cj is derived from (12). Nd and Vbi are then calculated from the linear regression in (13). After that, Cp is increased and the above regression is repeated, until the best correlation coefficient is achieved. Rp is extracted at reverse bias at high frequency. Derived from (14), the imaginary part of the diode admittance is given in (17), from which Rp is determined. So far, all the RF parameters are also obtained.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion

Model Validation Schottky diodes Fabricated in 65nm and 130nm CMOS Measured up to 67GHz Modeling root-mean-square errors < 5% In order to evaluate the model along with its parameter extraction, polysilicon-gate-separated Schottky diodes are fabricated in 65nm and 130nm CMOS technology and then measured up to 67GHz. As shown later, the modeled results correlate very well with the measured data, with all the root-mean-square errors less than 5%.

Model Validation DC forward characteristics Fig. Measured (red) and modeled (blue) DC characteristics of a single-cell diode in 65nm CMOS, with 0.92μm2 Schottky contact area. Results given by Schottky equation (black) are also given. (a) Forward I-V. (b) Forward R-V. (c) Reverse I-V. (d) Reverse R-V. This slide shows the measured and modeled DC characteristics at forward bias. The results given by Schottky equation are also given for comparison. The effectiveness of the bias-dependent series resistance is clearly demonstrated.

Model Validation DC reverse characteristics Fig. Measured (red) and modeled (blue) DC characteristics of a single-cell diode in 65nm CMOS, with 0.92μm2 Schottky contact area. Results given by Schottky equation (black) are also given. (a) Forward I-V. (b) Forward R-V. (c) Reverse I-V. (d) Reverse R-V. Shown in this slide is the DC characteristics at reverse bias. We cannot predict these characteristics at all if we use only Schottky equation, and the tunneling modeling is necessary.

Model Validation RF characteristics Fig. Measured (red) and modeled (blue) RF characteristics of a single-cell diode in 65nm CMOS, with 0.92μm2 Schottky contact area. (a) Ctotal=Im(Y)/ω versus bias at different frequencies. (b) Ctotal versus frequency at different biases (from -1.1V to 0.1V, 0.1V step). This slide gives the RF characteristics. The left figure is the total capacitance versus bias at different frequencies, and the right one is that versus frequency at different biases.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion

Model Scalability Scaling relations Cut-off frequencies N: the number of diode cells A: the area of Schottky contact Cut-off frequencies ~2THz in 65nm CMOS ~1THz in 130nm CMOS The extracted Rs and Cj together with the cut-off frequency estimated by Rs and Cj at zero bias will soon be illustrated in the slides. Before that, let’s directly get to the conclusion, and the conclusion is that good scalability with the number of diode cells N and the area of Schottky contact A is exhibited, and their relations are described in this slide. The cut-off frequency is around 2THz in 65nm CMOS and around 1THz in 130nm CMOS.

Model Scalability Scalability with the number of diode cells Fig. Model scalability with the number of diode cells in 65nm CMOS. Schottky contact area of a single cell is 0.185μm2. Here shows the model scalability with the number of diode cells.

Model Scalability Scalability with the area of Schottky contact Fig. Model scalability with the area of Schottky contact in 65nm CMOS. Devices under test are single-cell diodes. And Here shows the model scalability with the area of Schottky contact.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion

Discussion On forward capacitance Abnormal decreasing capacitance with increasing bias Suggested mechanisms Capture-emission of carriers by trap levels [8] Carrier transient response [9] Carrier polarization [10] Poole-Frenkel effect [11] Interface-state effect [12] We are focusing on the modeling of this behavior Now, I’d like to discuss a little about the complicated forward capacitance. The measured C-V data at forward bias often exhibits abnormal characteristics, most notably the decreasing capacitance with the increasing bias, which is not consistent with the standard diffusion capacitance theory. In the last decade, a number of researches have been done to identify the physical mechanisms behind it, and some suggested mechanisms reported are listed in this slide. And we are still working on the modeling of this behavior. [8] L. F. Feng et al., Appl. Phys. Lett., vol. 101, no. 23, pp. 233506-1–233506-4, Dec. 2012. [9] K. Bansal et al., Appl. Phys. Lett., vol. 105, no. 12, pp. 123503-1–123503-4, Sep. 2014. [10] D. Korucu et al., J. Optoelectron. Adv. Mater., vol. 11, no. 2, pp. 192–196, Feb. 2009. [11] W. Yang et al., Phys. Status Solidi, vol. 11, no. 3–4, pp. 714–717, Apr. 2014. [12] P. Chattopadhyay and D. P. Haldar, Appl. Surf. Sci., vol. 171, no. 3–4, pp. 207–212, Feb. 2001.

Outline Motivation Model Description Parameter Extraction Model Validation Model Scalability Discussion Conclusion

Conclusion A complete DC and RF model of CMOS Schottky diodes and its parameter extraction strategy are (will be) established. With different current transport mechanisms including thermionic emission, carrier velocity saturation and tunneling together with stray capacitance and inductance taken into account, the model predicts accurate results within 5% error, when evaluated with measurements up to 67GHz in 65nm and 130nm CMOS. The model is scalable with the number of diode cells and the area of Schottky contact. The model can be applied in mm-wave circuit design. With the modeling of the forward capacitance done, a complete DC and RF model of CMOS Schottky diodes and its parameter extraction strategy will be established. With different current transport mechanisms including thermionic emission, carrier velocity saturation and tunneling together with stray capacitance and inductance taken into account, the model predicts accurate results within 5% error, when evaluated with measurements up to 67GHz in 65nm and 130nm CMOS. The model is scalable with the number of diode cells and the area of Schottky contact. And the reliability of applying the model in millimeter-wave circuits is guaranteed.

Thanks for your attention! Wenyuan Zhang, Yang Tang and Yan Wang Tsinghua University June 21st 2019 That’s for my presentation. Deep thanks for your attention!