VirtualClock

Virtual Clock (VC) Proposed by Lixia Zhang (PhD thesis 1989, Sigcomm 1990) Goal: A scheduler that emulates a system with transmissions in periodic intervals Two state variables for each flow j: auxVCj virtual transmission time of the flow rj reserved rate The variable auxVCj keeps track of hypothetical departure times. If all traffic from flow j is limited to the reserved rate, then auxVCj is the departure time of an arrival. Upon arrival of a packet from flow j with size Ljk at time ajk: auxVCj = max (auxVCj , ajk ) + Ljk / rj Stamp auxVCj in packet header Packet are transmitted in increasing order of virtual transmission times

Virtual clock order (with auxVCi) Example: Virtual Clock (with place holder) C = 1 Mbps, r1=r2=r3=1/3 Mbps, L=1000 bits wall clock (ms)= 1 3 4 6 7 8 9 2 5 10 11 1 2 3 4 5 6 7 8 9 10 11 r1=1/3 auxVC1 1 2 3 4 5 6 7 8 9 10 11 12 time r2=1/3 auxVC2 1 2 3 4 5 6 7 8 9 10 11 12 time r3=1/3 auxVC3 1 2 3 4 time Virtual clock order (with auxVCi) time

Example: Virtual Clock C = 1 Mbps, r1=r2=r3=1/3 Mbps, L=1000 bits wall clock (ms)= 1 3 4 6 7 8 9 2 5 10 11 r1=1/3 auxVC1= 1 2 3 4 5 6 7 8 9 10 11 12 time 3 6 9 12 15 18 r2=1/3 auxVC2 = 1 2 3 4 5 6 7 8 9 10 11 12 time 3 6 9 12 15 18 r3=1/3 auxVC3 = 1 2 3 4 time 3 6 9 12 Virtual clock order (with auxVCi) 1 1 1 2 2 2 3 3 3 4 4 4 time 3 3 3 6 6 6 9 9 9 12 12 12

Virtual clock order (with auxVCi) Example: Virtual Clock (with place holder) C = 1 Mbps, r1=r2=r3=1/3 Mbps, L=1000 bits “auxVCj = max (auxVCj , ajk ) + Ljk / rj” prevents credit accumulation of idle flows wall clock (ms)= 1 3 4 6 7 8 9 2 5 10 11 r1=1/3 auxVC1 1 2 3 4 time r2=1/3 auxVC2 1 2 3 4 time r3=1/3 auxVC3 1 2 3 4 time Virtual clock order (with auxVCi) time

Virtual clock order (with auxVCi) Example: Virtual Clock (complete) C = 1 Mbps, r1=r2=r3=1/3 Mbps, L=1000 bits “auxVCj = max (auxVCj , ajk ) + Ljk / rj” prevents credit accumulation of idle flows 1 3 4 6 7 8 9 2 5 10 11 wall clock (ms)= r1=1/3 auxVC1 1 2 3 4 time 3 6 9 12 r2=1/3 auxVC2 1 2 3 4 time 3 6 9 12 r3=1/3 auxVC3 1 2 3 4 time 9 12 15 18 Virtual clock order (with auxVCi) 1 1 2 2 1 3 3 2 4 4 3 4 time 3 3 6 6 9 9 9 12 12 12 15 18

Problem with Virtual Clock (with place holder) Flow that gets more than reserved rate may be penalized in the future 1 3 4 6 7 8 9 2 5 10 11 9 10 11 r1=1/3 auxVC1= 1 2 3 4 5 6 7 8 time 3 6 9 12 15 18 21 24 r2=1/3 auxVC2 = 1 2 3 4 time 8 11 14 17 r3=1/3 auxVC3 = 1 2 3 4 time 8 11 14 17 Virtual clock order (with auxVCi) time

Problem with Virtual Clock (with place holder) Flow that gets more than reserved rate may be penalized in the future 1 3 4 6 7 8 9 2 5 10 11 r1=1/3 auxVC1= 1 2 3 4 5 6 7 8 time 3 6 9 12 15 18 21 24 r2=1/3 auxVC2 = 1 2 3 4 time 8 11 14 17 r3=1/3 auxVC3 = 1 2 3 4 time 8 1 14 17 1 2 3 4 5 1 1 2 2 3 3 4 4 6 7 8 Virtual clock order (with auxVCi) time 3 6 9 12 15 8 8 11 11 14 14 17 17 18 21 24 time

Discussion The “penalty” of service in VirtualClock can be viewed as a fairness issue Note that WFQ timestamps essentially replace the wall-clock arrival time with the arrival time in system virtual time Using network calculus methods, we can see that the root of the problem is that rate guarantees of Virtual Clock are too weak (so it is not a fairness issue) VirtualClock = SCED with lower service curve S(t) = r t ”Penalty” is inherent to lower service cuves of the form S(t) = r t This motivates to look for: Service curves that that offer stronger rate guarantees (strong sc, adaptive sc) Schedulers that realize these service curves (PSRG)