Embedded Image Processing: Edge Detection on FPGAs Orin Harris • Islande Belizaire • Wadner Joseph • James Haralambides, PhD Abstract The Reader 24-bit color 3-bit color Edges Detected The Reader contains three processes: Set Enable, Enable Normal, and Edge Detection. The operations performed by the system depend on the process that is currently running. The Set Enable process determines which region on the screen is currently active based on a row and column coordinates it receives from the VGA Controller. The result of the Set Enable process determines whether the Reader should enter into Enable Normal or Edge Detection mode. When the Reader is in Enable Normal mode, image pixels retrieved from memory are sent to the Multiplexer or the Encryption component without any modification. During the Edge Detection mode, the pixel color intensities are manipulated by the Reader to determine the existence of edges. In order to identify edges three pixels have to be compared: the current pixel, the previous pixel in the same row and the corresponding pixel in the previous row. However, since pixel retrieval from memory needs to be synchronized with the VGA controller, non-sequential access of pixels is not possible. To maintain information of pixels in the previous row, a buffer is created to store the previous row’s pixel values. If the current pixel is different from either the previous pixel in the same row or the corresponding pixel in the previous row (stored in the buffer), then the current pixel is colored white to indicate the presence of an edge. The Reader sends data either to the Multiplexer either directly or through the Encryption component. Embedded Image Processing - Edge Detection on FPGAs Edge detection in image processing is the process of identifying sharp intensity transitions in images that are edited on the pixel level. Such transitions may be identified by computing intensity differences of neighboring pixels. The process is improved by taking into consideration the direction of such transitions using the image’s gradient component. Image processing applications are computationally intensive as processing of images takes place on individual pixels or groups of pixels repeatedly. Field Programmable Gate Arrays (FPGAs) have an inherent degree of parallelism since the gate array is a collection of fine grain processing elements. In this project, we will implement the above mentioned edge detection technique using an FPGA board, namely, the Spartan 3E board. Schematic of the Circuit To implement Edge Detection on FPGA boards , a VHDL code had to be generated and embedded on the Spartan 3E board. The main components of the circuit are: the Clock, the Reader, Multiplexer, Encryption component, ROM memory, and VGA Controller. Edge Detection Edge detection involves comparing the intensity of vertical and horizontal neighboring pixels to determine whether an edge exists. To do this, two formulas were employed which are represented as two filters, a horizontal and a vertical filter. These filters work as follows: if pixel one’s intensity is different than pixel two’s intensity by a pre-determined threshold, then there is an edge and pixel one is colored white to intensify the edge. However, if the difference is below the threshold, then there is no edge and pixel one is colored black. Due to color depth limitations imposed by the Spartan 3E board, images are viewed using 3-bit color representations, therefore the difference between color components of any two pixels will be either 0 or 1. The Multiplexer The Multiplexer uses the results of the Set Enable process of the reader component to determine whether to pixels of the original image or those of the imaged produced through edge detection are forwarded to the VGA Controller. The Encryption Component The Encryption component produces different colorization schemes for the image produced by edge detection to enhance visibility. Horizontal Derivative formula The VGA Controller Circuit Schematic The Clock The VGA controller displays the images on the screen and operates at 25 Mhz. The frequency of the clock is a key factor in the design. Synchronization of the reader and memory components to the VGA component is required in order to synchronize pixel retrieval , pixel processing, and pixel display. Vertical Derivative formula This sequential circuit needs a clock to synchronize its operations. The clock operates at 25 MHz which the Reader and the VGA require in order to perform the edge detection algorithm and display the image on the screen effectively. ROM Memory Vertical Filter Horizontal Filter The memory component is a single port read-only memory (ROM). 256 x 256 images are stored using a word size of 3 bits (color depth of 8 colors) and a word depth of 65,536 words (216 words). VGA Pin Assignment ROM memory