for BESIII MDC electronics Huayi Sheng The preliminary design for BESIII MDC electronics Huayi Sheng On behalf of MDC electronics group June 5, 2002 IHEP, Beijing

I. Design goal II. Design considerations III. Design scheme IV. Summary

I. Design goal After a series of processing in system, To receive the signals from 9096 sense wires. After a series of processing in system, to send the acquired data to DAQ. ● Charge measurement  dE/dx ● Time measurement  track / moment. ● To provide fired information  Trigger .

▲ charge resolution ENC ● charge measurement ▲ charge resolution ENC e = 6% is required for system ee (electronics) = 15% × de (MDC itself) So ee = 0.9% Keep 47 layers of sense wires and 70% truncation in mind, So for a single electronics channel’s resolution ENC: So ENC = 5.2% For MIP , most probable energy loss = 100 fc So ENC = 5 fc

▲ Charge dynamic range : 15fc—1800fc ▲ Charge INL : 2% (15fc--1800fc)

▲ time resolution t ● Time measurement A single wire: dp ≤ 125 m The required System spatial resolution: 130m A single wire: dp ≤ 125 m So for a single electronics channel: ep = 35.7m For MDC, electron drift velocity ≈ 30m/ns So the time resolution for a single channel will be: t ≤ 1.2 ns We take t ≤ 0.5 - 1 ns

Which factors contribute to the t ? ① The length of e- and e+ bunches in Z direction. z = 1.5cm Uncertainty of collision moment ： t1 35 ps Negligible ! ② The timing error caused by time walk . t2 ≤ 1ns It can be corrected by off-line using charge value. ③ The time measurement error t3 of TDC. It is possible to get t3≤0.5ns using CERN HPTDC. .

▲ Time range : 0—400 ns ▲ Time INL: 0.5%

II. Design considerations ●　BEPCII Multi-bunch running. Bunch crossing = 8ns. L1 = 3.2 s. 　　 Pipeline technique must be used . ●　BEPCII Lum ＝1×1033/cm2/s  Large quantity data to be acquired; 　  Multi-stage parallel processing must be adopted, So as to reduce system dead time. ● MDC: small cell configuration. size ～14mm×14mm. Simulation shows： ■ Max. drift time: td_max = 400 ns Max. signal width: tw_max = 650 ns

a number of 1/t waveforms formed by a single ionized electron. ■ The output signal of sense wire is a pile-up of a number of 1/t waveforms formed by a single ionized electron. ● The signal rate for a single wire： 30K / S

III. Design scheme Four types of modules/cards: 1. Preamplifier cards; 2. SDQT modules; 3. Calibration modules; 4. Logic control modules.

Simplified MDC electronics block diagram

1. Preamplifier ① A transimpedance type. Band width : 70MHz—80MHz 。 ② Low power dissipation. ＜30mw. ③ Differential output, capable of driving long cable(18m). ④ A piece of hybrid per channel. ⑤ 8 ch / card (～10cm×6cm). Most cards will be directly mounted on endplate. Some inner cards will be mounted 0.5m-1m away from endplate, with soft printed strip connecting card to feedthrough. ⑥ Take BESII MDC preamp. as baseline design with some modifications.

SDQT Module ⑴《Amplification+Shaping+discrimination》circuitry ▲ To split the signal into two branches. ▲ Time branch: using leading edge discrimination to give the arrival time ▲ Charge branch: signal shaping to fit the charge measurement.

How to shape the signal？ It depends on the scheme used for Q measurement. A numeric integral method based on FADC will be used for Q measurement: Successively digitize the analog signal with FADC, Make a numeric integral over digitized data; The result represents the charge of waveform. How to determine the integral width? It depends on the pile-up probability of signal. The signal rate (fired rate) of a single wire ～ 30k/s. According to Poisson probability formula We get a relation between pile-up and interval △t :

The integral width can be setup to be 1μs, the pile-up probability : ＜3 % . “drift time + shaped signal width ”  1μs

Three-stage shaping: First stage: Pole zero shaping to cancel long tail formed by preamp and long cable; Second stage: a simple RC shaping to make waveform smooth; Third stage: Pole zero shaping to cancel long tail formed by RC shaper.

⑵ Charge measurement circuitry FADC-based pipeline scheme. Numeric Integral to acquire charge value. Simulation showed： The FADC with 40MHz-10bit can fully fulfill the requirement for Q measurement.

Block diagram for Q measurement

One Local FPGA can cope with 4 or 8 channels. Pipeline length: Where +1 is for getting pedestal value just prior to t = t One Local FPGA can cope with 4 or 8 channels.

⑶ Time measurement circuitry To measure the time interval between t and the arrival time of wire signal. It covers three sub-intervals： ① Flight time of particle from collision point to a cell. A random value. ② The drift time of ionized electron which is nearest to a sense wire. This time is exactly one we need to measure. ③ The transfer time of signal from avalanche point on wire to input of preamp. A random value too. The contributions from ① and ③ will be given by offline correction.

Scheme for time measurement： Using CERN HPTDC as key component.  □     Dead time free. □     32 channels/chip。 Size～2.7×2.7 cm2 。 □     External clock：40MHz。Synchronized to bunches. □     Time resolution： ～ 250ps RMS low resolution mode ～ 70ps RMS medium resolution mode ～ 35ps RMS high resolution mode ～ 15ps RMS very high resolution mode (8ch per chip)。 □     Double pulse resolution：5ns (typical); 10ns (guaranteed). □     Separate leading or trailing edge measurement; Simultaneous measurement of leading edge and pulse width (not true for very high resolution mode). □     Zero suppression and address assembly inside chip.

How does the HPTDC work? HPTDC covers: a coarse time counter, a fine time counter a PLL, a DLL. ◆ PLL performs multiplication of external 40MHz clock to 40MHz, 160MHz, 360MHz. ◆ Coarse time counter choose one of above three clocks as its working clock to record the integer number N of clock between t and hit signal. ◆ DLL turns the working clock into a high frequency clock . ◆ Fine time counter works on high frequency clock and performs measuring the fractional part f of a clock . ◆ ( N+f ) delivers the drift time to be measured.

⑷ Threshold voltage circuitry. Used for on board 32 discriminators.

How to readout Q and T data ？ ◆ To design the SDQT module according to 9U-VME64 standard. ◆ To set up a Global buffer to store Q and T data in each SDQT module. ◆ To implement the function of Global buffer using a FPGA called as Global FPGA. ◆ To adopt BLT readout mode. ◆ To read out the data from the Global buffer every other 60 Triggers.

Data readout from SDQT module

3. Calibration modules. Used to calibrate the whole system. Logic control and fan out / fan in modules. Used to make the system working in order.

IV. Summary Preamp., SDQT, Calibration, Logic control. ● System consists of 4 types of modules/ cards: Preamp., SDQT, Calibration, Logic control. ● The SDQT module will be designed according to 9U-VME64 standard. Each SDQT module covers： 32 ch. of “amp. + shaping +Disc”； 32 ch. of Charge measurement circuitry； 32 ch. of time measurement circuitry; A programmable threshold voltage generator. ● The numeric integral is used for Q measurement.

zero suppression on board much simple. ● Use of FPGA makes the charge extraction and zero suppression on board much simple. without introducing any additional dead time. ● CERN HPTDC chip will be used for T measurement. ● All the functions in FPGA will be performed by programming VHDL language; It brings flexibility to modifying the functions without changing hardware.

Thank you!