Fault-tolerant Multicore System on Network-on-Chip

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Presentation transcript:

Fault-tolerant Multicore System on Network-on-Chip Presenter: Parhelia

Motivation (1) Challenge of future SoC: Performance/Technology Gap Advanced architecture techniques are required! Before 2002, ILP helped to close the gap successfully

Motivation (2) Key for Multicore:Interconnection Trend: More Core, More better Single core with increased performance 2002, Pentium 4 Northwood 1997, Pentium MMX 1997, Pentium II 1993, Pentium 1999, Pentium III 2001, Tualatin Key for Multicore:Interconnection Multicore processor with more and more cores!! 2005, Pentium D 2006, Core 2 Duo (Conroe) 2006, Core 2 Quad (Kentisfield) 2007, TeraScale 80-core prototype

Motivation (3) Future on-chip communication for SoC IPs OCN (On-Chip Network) is a novel and practical approach to interconnect SoC IPs

Fault-Tolerant NoC(1) Device size shrinking Erroneous in production

Fault-Tolerant NoC (2) Just like normal computer network :p Model a faulty node to multiple data paths Define relative FT routers architectures and FT routing algorithms.

Goal (1) Demonstrate FT NoC on real application using FPGA GUI interface Visual demonstration See performance degradation

Goal (2) Demonstrate FT NoC on real parallel application Rendering engine FPGA

What you will learn is… Prerequisite State-of-the-Art on-chip communication technology HW/SW co-design FPGA emulation concepts and experiences Prerequisite Programming language (C/C++, GUI better) Concepts on digital logic design Creativity, smart-working Contact Information 黃耿賢 time@access.ee.ntu.edu.tw Software / system simulation 許展誠 parhelia@access.ee.ntu.edu.tw Hardware design / FPGA Emulation

Reference [1] L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” on Computer, pp. 70-78, Vol. 35, Issue. 1, Jan. 2002. [2] http://techresearch.intel.com/articles/Tera-Scale/1449.htm [3] http://www.tilera.com/pdf/ProBrief_Tile64_Web.pdf [4] S. Murali,, N. Vijaykrishnan, M.J. Irwin, L. Benini, and G. De Micheli, “Analysis of error recovery schemes for networks on chips,” IEEE Design & Test of Computers, pp.434-442, Volume 22, Issue 5, Sep. 2005. [5] N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, and F. Catthoor, “A Complete Network-On-Chip Emulation Framework,” Proceedings of the conference on Design, Automation and Test in Europe (DATE’ 05), pp.246-251, Vol.1, 2005.