Observation of an anomalous minority carrier trap in n-type InGaAs   Tim Gfroerer and Kiril Simov Davidson College, USA Mark Wanlass National Renewable Energy Lab, USA ~ Supported by Bechtel Bettis, Inc. and the American Chemical Society – Petroleum Research Fund ~

Defect characterization via DLTS + + Depletion Layer With Bias Depletion Layer With Bias Depletion Layer With Bias - + Temporary Reduced Bias - Temporary Reduced Bias + - + + + - + + - + + + + + - + P+ + + + N - + - + + + + + + + + - - + + - + + We have used temperature-dependent transient capacitance measurements, more commonly known as deep level transient spectroscopy (DLTS), to explore the distribution of defect levels in In0.53Ga0.47As p+/n diodes. As the negative side is sparsely populated, the depletion layer extends much further into the negative side, as indicated in the drawing. The DLTS experiment involves applying a bias pulse that expands the depletion layer, which changes the capacitance of the device. This gives the mobile charge carriers a chance to move to a new region of the diode. Once they get to this new region, there is the possibility that they will be trapped. By measuring the time it takes for the capacitance to change, we study how charges move into and out of traps, and the capture cross section and the depth of the traps can be determined.

Typical DLTS Measurements

Experimental Setup (5) (1) (2) (4) (3) Computer with LabVIEW Temp Controller Pulse Generator Cryostat with sample Digital Scope (Tektronix) (1) (2) (3) (4) (5) Oxford 77K Agilent Capacitance meter (Boonton) Here is a diagram of the setup for the experiment. The first step of the acquisition process is initiated by a computer running LabVIEW, a graphical programming language that facilitates instrument control. The computer sends a signal to the temperature controller to set the new temperature. Once the temperature stabilizes, we proceed to step two. The pulse generator sends a bias pulse train to the diode. The response is measured by a capacitance meter and averaged on a digital oscilloscope. Capacitance measurements are made with a Boonton 7200 Capacitance Meter, which uses a 1MHz test signal and has a response time of approximately 30ms. After the data sampling is over, the data is sent to and stored on the computer. Then the next temperature is tested.

Device Structure and Band Diagram { The nominal device structure is presented in Fig. 1 and the associated band diagram is shown in Fig. 2.

Transient Capacitance: Escape The sign of the capacitance transients in Fig. 3 indicates that minority carriers are being trapped during the +0.1V filling pulse when the bias is increased (i.e. made less negative). The observation of a minority carrier trap under reverse bias conditions is unusual, but may be explained by changes in the occupation of hole traps in the n-type material near the p+/n junction (model to be described later). We observe a temperature independent escape mechanism at low temperature. As shown in Fig. 4, thermal activation out of the traps becomes less important with falling temperature, giving way to a constant escape time tesc of approximately 110 ms. We attribute this temperature-independent phenomenon to tunneling through the narrow (on the order of 10nm according to SimWindows2 modeling) barrier that separates holes in the p-type region from adjacent trap states.

Filling Pulse Dependence: Capture We note a puzzling symmetry between the trap capture and escape times. Let DCtraps(t) be the amplitude of the slow capacitance transient for a filling pulse of length t (see Fig. 5) and let DC0 be the saturated amplitude obtained with a suitably long filling pulse. Then DC0 – DCtraps(t) is proportional to the fraction of unfilled traps and the capture time tcap is obtained from the slope of the plot presented in Fig 6. We find that tcap ~ tesc, and we attribute this symmetry to the similarity of the barrier for the capture and escape processes.

Proposed Model Our results may be explained by changes in the occupation of hole traps in the n-type material near the p+/n junction as shown in Fig. 7. A similar model has recently been proposed to account for minority carrier trapping in Schottky-barrier p-type GaAsN under reverse bias.1 In our case, when the bias is increased the intersection of the trap level with the hole quasi-Fermi energy shifts away from the junction, permitting more holes to be trapped. 1 S.W. Johnston, S.R. Kurtz, D.J. Friedman, A.J. Ptak, R.K. Ahrenkiel, and R.S. Crandall, Appl. Phys. Lett. 86, 72109 (2005).

Testing the Model In order to test the validity of our model, we consider how DC0 depends on the applied bias V. We use SimWindows modeling to determine how d changes with bias, yielding the thickness of material probed in each experiment. If the traps are located near the junction, we expect the saturated amplitude of the capacitance transient associated with these traps to scale with this thickness. Results of these calculations are shown in Fig. 8 along with a scaled measurement of DC0(V). For comparison, we use our measurement of capacitance vs. voltage at T = 145K to estimate how the depletion thickness W changes with applied bias. If the trapping process is related to changes in trap occupation near the edge of the depletion region (as is usually the case in DLTS experiments), we would expect DC0(V) to scale with this parameter. Since the transient amplitude follows the change in d rather closely, and deviates considerably from the change in W, we conclude that our model is correct: the minority carrier traps are located near (i.e. within tens of nanometers of) the p+/n junction.

Conclusions 0.29eV hole trap is observed in n-type InGaAs under reverse bias Temperature-dependent capture and escape rates are symmetrical Rates level off at cold temperatures due to tunneling Device modeling points to defect states near the p+/n junction