Topics Bus interfaces. Platform FPGAs.

Bus interfaces Requirements: Techniques: High performance. Variable signal environment. Techniques: Asynchronous logic. Handshaking-oriented protocols.

Timing diagrams 1 a changing stable b Timing constraint c

Asynchronous logic Distribute timing information with values. No global clock. Clock signal paths must have the same delay as data values.

Latching an asynchronous signal adrs D Q adrs adrs_ready

Asynchronous timing constraints Must satisfy setup, hold times. adrs Setup time Hold time

Bus system design Requirements: Constraints: Imposed by the other side of the system. Constraints: Imposed by this side of the system. requirements a b constraints

Views of the bus Hardware: a b D Q D Q Combinational logic

Views of bus system, cont’d. Timing diagram: x y b a D Q Combinational logic x y

Bus protocols Basic transaction: four-cycle handshake. a b

Handshake machine Each side is an FSM (possibly asynchronous): a b Go enq enq 1 1 ack ack ack

Basic protocols Handshake transmits data:

Box 1 logic

Box 2 logic

Bus timing t1 = tc1 - td1 >= tr td1 = d stable td2 = d not stable tc1 = c rises t2 = tack1 - tc1 >= th tc2 = c falls t3 = tc2 - tack1 >= th tack1 = ack rises

Busses and systems Microprocessor systems often have several busses running at different rates: CPU mem High-speed bridge I/O Low-speed

Basic signals in a bus

Bus characteristics Physical Electrical Protocol Connector size, etc. Voltages, currents, timing. Protocol Sequence of events.

Advanced transactions Multi-cycle transfers: Several values on one handshake. May use implicit addressing.

PCI bus Used for box-level system interconnect. Two versions: 33 MHz. 66 MHz. Supports advanced transactions.

PCI bus read

Multi-rate systems Logic blocks running at different clock rates may communicate: Multi-chip. Single-chip. Slow bus connects to fast logic. Logic 1 Logic 2 100 MHz 33 MHz

Metastability Registers capturing transitioning signals may take an arbitrarily long time to settle.

Resynchronization Use cascaded registers to minimize the chance of using a metastable value. d D Q D Q dout f

Platform FPGAs Put all the logic for a system on one FPGA. Requires large FPGAs plus: Specialized logic: I/O support; memory interface. CPUs.

Example: Virtex II Pro Major features: Large FPGA fabric. High-speed I/O. PowerPC.

Virtex II Pro High-speed I/O Rocket I/O: parallel/serial or serial/parallel transceiver. Clock recovery circuitry. Transceivers for multiple standards: Gigabit Ethernet, Fibre Channel, etc. Programmable decoding features. Interface to FPGA fabric.

Virtex II Pro CPUs Up to 4 PowerPC 405s per chip: 5 stage pipe, static branch prediction, etc. Separate instruction, data caches. MMU. Timers. Scan-based debug support.

PowerPC CoreConnect

Altera Stratix Combines FPGA fabric, memory blocks, multipliers.

Stratix DSP block