Coordination meeting Sept 24, 2009.

Slides:

Advertisements

Similar presentations

STA CCD Detector, Controller, and System Developments

Advertisements

Trigger, DAQ, calibration Robert Sulej, październik 2007.

Front-end electronics for Time Projection Chamber I.Konorov Outlook:  TPC requirements  TPC readout options  Options for TPC FE chips  Prototype TPC.

General Electronics for Time projection chambers GET a Multi-Project for IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, York General Electronics.

Systems for Nuclear Physics Today 1.Number of Channels Approx. 1,000 2.Short & Reconfigurable Experimental Setups with variety of Detector Types 3.Human.

Laser Tracking System (LTS) Son Nguyen Jassim Alshamali Aja ArmstrongMatt Aamold.

Tullio Grassi ATLAS–CMS Power Working Group 31 March 2010 DC-DC converters and Power Supplies requirements for CMS HCAL Phase 1 Upgrade.

9th October 2008AIDA FEE progress report P.J.Coleman-Smith 1 AIDA Frontend Electronics progress report. Mezzanine to FEE64 connection. Mezzanine Layout.

Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control.

By: Daniel BarskyNatalie Pistunovich Supervisors: Rolf HilgendorfInna Rivkin.

Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

Digital Signal Processing and Generation for a DC Current Transformer for Particle Accelerators Silvia Zorzetti.

AIDA FEE64 development report August 2010 Progress after Texas CAD work Manufacturing 25th August

1 Outer Tracker Front-End Layout Distribution of Signals and Bias NIKHEF/HeidelbergOctober 2002.

SPD Control Board 16th February SPD Control Board (VFE control and SPD multiplicity) VFE’s control (I2C communication: SDA,SCL; clock; reset/trigger.

TRIO-CINEMA 1 UCB, 2/08/2010 Cinema Stein Interface FPGA (CSI) [Part II] Karthik Lakshmanan CINEMA - EE Team Space Sciences Laboratory University of California,

The AFTER electronics from a user’s point of view D. Attié, P. Colas Mamma meeting,CERN Feb T2K electronics.

HBD FEE test result summary + production schedule 16mv test pulse result –5X attenuator + 20:1 resistor divider at input (to reduce the noise on the test.

LIGO-G Z Detector Characterization Software Tools K. Riles - University of Michigan 1 Status Report on CW Discriminator Work Keith.

Team 2 Yimin Xiao Jintao Zhang Bo Yuan Yang.  The project we propose is a digital oscilloscope with playback function that provides almost any function.

New PSB Beam Control Upgrade of daughter cards Alfred Blas PSB rf Working group meeting 24/03/ Generation of REV clocks 2.Synchronization with.

6th Summer School on “ADC & DAC Metrology” PETRČESÁK Czech Technical University PhD Student Analysis of the system for dynamic ADC testing.

ERC - Elementary Readout Cell Miguel Ferreira 18 th April 2012

Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.

M M M M 5. Not Listed

D. Attié, P. Baron, D. Calvet, P. Colas, C. Coquelet, E. Delagnes, R. Joannes, A. Le Coguie, S. Lhenoret, I. Mandjavidze, M. Riallot, E. Zonca TPC Electronics:

BPM stripline acquisition in CLEX Sébastien Vilalte.

9/12/2003Ivan Hruska1 First box prototype –Box design in July ‘03 –Box produced during August ’03 Tested last week in few fingers Small changes necessary.

Plans and Progress on the FPGA+ADC Card Pack Chris Tully Princeton University Upgrade Workshop, Fermilab October 28, 2009.

QIE10 development Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear.

Timing Board FPGA. Use existing IP version until firmware is ported to new FPGA FPGA Existing IP Carrier UCD Digital I/O TSG Timing Board.

Distributed Low Voltage Power Supply System for Front End Electronics of the TRT Detector in ATLAS Experiment E.Banaś a, P.Farthouat b, Z.Hajduk a, B.Kisielewski.

Standard electronics for CLIC module. Sébastien Vilalte CTC

Electronics Workshop GlueX Collaboration Meeting 28 March 2007 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Physics Division Topics: Review.

VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk.

1 Status report 2011/8/12 Atsushi Nukariya. 2 Progress ・ FPGA -> Revision is completed. -> Obtained data from front-end chip. ・ Software.

4 Channel DAC (Petri): 3 boards available for testing (version 1)-> now Transition board-> 22/12/2010 End of Hardware tests-> 28/01/2011 Attached DDC firmware.

GET is a relatively unique project in data capture for Nucl. Phys. because:- – G : for Generic – Multi national lab collaboration – Multi project application:-

October 12th 2005 ICALEPCS 2005D.Charlet The SPECS field bus  Global description  Module description Master Slave Mezzanine  Implementation  Link development.

ASAD Workshop Saclay (CEA Irfu) November 25, AGET circuit: Application Information actar.

MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.

LHCb Outer Tracker Electronics 40MHz Upgrade

Injector II Low Level RF & Interlock – Status

Status of NA62 straw readout

CLAS12 DAQ & Trigger Status

Kenneth Johns University of Arizona

Calorimeter Mu2e Development electronics Front-end Review

Mini-Summary of the CAEN 10-12th March Meeting

CRaTER Pre-Environmental Review (I-PER) Engineering Requirements/Design Updates Bob Goeke September 10-11, 2007.

Readout electronics for aMini-matrix DEPFET detectors

Iwaki System Readout Board User’s Guide

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

ETD/Online Report D. Breton, U. Marconi, S. Luitz

Christophe Beigbeder PID meeting

Firmware Structure Alireza Kokabi Mohsen Khakzad Friday 9 October 2015

IR detector for demonstrator and Readout

CoBo - Different Boundaries & Different Options of

ECE-L304 Lecture 3.

Electronics requirements for special diagnostics for the XFEL

Electronics: Demod + 4Q FE

Terry Cotter LO/IF Group Leader

Status of CO2 Cooling tests at CERN for Pixel phase 1

New PSB beam control rf clock distribution

FEE Electronics progress

CRaTER Pre-Environmental Review (I-PER) Engineering Requirements/Design Updates Bob Goeke September 10-11, 2008.

Testbeam status report

PID meeting Mechanical implementation Electronics architecture

Progress on the 40 MHz SEU Test System based on DE2 Board

Presentation transcript:

Coordination meeting Sept 24, 2009

AsAd Status Technical spec almost complete Componants tests ADC DAC Supply Monitoring FPGA

ADC Data test pattern frame clock 25MHz and frequency of the output bit clock 150MHz.

CDR Ready October 15 Cooling + EMC not yet defined Detector ZAP AsAd To CoBo Cooling Mechanical 3 m. maximum Cold plate Shield Supply

Planning

Test…..! Not so easy…manpower.. Functionnal Local manpower AND AGET T2K test Phase 1 Not so easy…manpower.. CENBG+GANIL+IRFU+MSU Basic version ML 507) hits AGET Phase 2 CENBG+GANIL+IRFU+MSU 4 AsAd + 1 CoBo Phase 3 Geographical distribution Does not help..