EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

Summary of Va > 0 current density eqns. Ideal diode, Jsexpd(Va/(hVt)) ideality factor, h Recombination, Js,recexp(Va/(2hVt)) appears in parallel with ideal term High-level injection, (Js*JKF)1/2exp(Va/(2hVt)) SPICE model by modulating ideal Js term Va = Vext - J*A*Rs = Vext - Idiode*Rs ©rlc L17-24Mar2011

Plot of typical Va > 0 current density equations ln(J) data Effect of Rs Vext VKF ©rlc L17-24Mar2011

For Va < 0 carrier recombination in DR The S-R-H rate (tno = tpo = to) is ©rlc L17-24Mar2011

Reverse bias (Va<0) => carrier gen in DR Consequently U = -ni/2t0 t0 = mean min. carr. g/r lifetime ©rlc L17-24Mar2011

Reverse bias (Va< 0), carr gen in DR (cont.) ©rlc L17-24Mar2011

Ecrit for reverse breakdown (M&K**) Taken from p. 198, M&K** ©rlc L17-24Mar2011

Reverse bias junction breakdown Avalanche breakdown Electric field accelerates electrons to sufficient energy to initiate multiplication of impact ionization of valence bonding electrons field dependence shown on next slide Heavily doped narrow junction will allow tunneling - see Neamen*, p. 274 Zener breakdown ©rlc L17-24Mar2011

Reverse bias junction breakdown Assume -Va = VR >> Vbi, so Vbi-Va-->VR Since Emax~ 2VR/W = (2qN-VR/(e))1/2, and VR = BV when Emax = Ecrit (N- is doping of lightly doped side ~ Neff) BV = e (Ecrit )2/(2qN-) Remember, this is a 1-dim calculation ©rlc L17-24Mar2011

Junction curvature effect on breakdown The field due to a sphere, R, with charge, Q is Er = Q/(4per2) for (r > R) V(R) = Q/(4peR), (V at the surface) So, for constant potential, V, the field, Er(R) = V/R (E field at surface increases for smaller spheres) Note: corners of a jctn of depth xj are like 1/8 spheres of radius ~ xj ©rlc L17-24Mar2011

BV for reverse breakdown (M&K**) Taken from Figure 4.13, p. 198, M&K** Breakdown voltage of a one-sided, plan, silicon step junction showing the effect of junction curvature.4,5 ©rlc L17-24Mar2011

Diode equivalent circuit (small sig) ID h is the practical “ideality factor” IQ VD VQ ©rlc L17-24Mar2011

Small-signal eq circuit Cdiff and Cdepl are both charged by Va = VQ Va Cdiff rdiff Cdepl ©rlc L17-24Mar2011

Diode Switching Consider the charging and discharging of a Pn diode (Na > Nd) Wn << Lp For t < 0, apply the Thevenin pair VF and RF, so that in steady state IF = (VF - Va)/RF, VF >> Va , so current source For t > 0, apply VR and RR IR = (VR + Va)/RR, VR >> Va, so current source ©rlc L17-24Mar2011

Diode switching (cont.) VF,VR >> Va F: t < 0 Sw RF R: t > 0 VF + RR D + VR ©rlc L17-24Mar2011

Diode charge for t < 0 pn pno x xn xnc ©rlc L17-24Mar2011

Diode charge for t >>> 0 (long times) pn pno x xn xnc ©rlc L17-24Mar2011

Equation summary ©rlc L17-24Mar2011

Snapshot for t barely > 0 pn Total charge removed, Qdis=IRt pno x xn xnc ©rlc L17-24Mar2011

I(t) for diode switching ID IF ts ts+trr t - 0.1 IR -IR ©rlc L17-24Mar2011

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Ideal diode equation for EgN = EgN Js = Js,p + Js,n = hole curr + ele curr Js,p = qni2Dp coth(Wn/Lp)/(NdLp), [cath.] = qni2Dp/(NdWn), Wn << Lp, “short” = qni2Dp/(NdLp), Wn >> Lp, “long” Js,n = qni2Dn coth(Wp/Ln)/(NaLn), [anode] = qni2Dn/(NaWp), Wp << Ln, “short” = qni2Dn/(NaLn), Wp >> Ln, “long” Js,n<<Js,p when Na>>Nd , Wn & Wp cnr wdth ©rlc L17-24Mar2011

Ideal diode equation for heterojunction Js = Js,p + Js,n = hole curr + ele curr Js,p = qniN2Dp/[NdLptanh(WN/Lp)], [cath.] = qniN2Dp/[NdWN], WN << Lp, “short” = qniN2Dp/(NdLp), WN >> Lp, “long” Js,n = qniP2Dn/[NaLntanh(WP/Ln)], [anode] = qniP2Dn/(NaWp), Wp << Ln, “short” = qniP2Dn/(NaLn), Wp >> Ln, “long” Js,p/Js,n ~ niN2/niP2 ~ exp[[EgP-EgN]/kT] ©rlc L17-24Mar2011

Bipolar junction transistor (BJT) E B C VEB VCB Charge neutral Region Depletion Region The BJT is a “Si sandwich” Pnp (P=p+,p=p-) or Npn (N=n+, n=n-) BJT action: npn Forward Active when VBE > 0 and VBC < 0 ©rlc L17-24Mar2011

npn BJT topology x x’ p-Base n-Collector N-Emitter z WB WB+WC -WE x”c Charge Neutral Region Depletion Region x x’ p-Base n-Collector N-Emitter z WB WB+WC -WE x”c x” xB x’E IE IC IB ©rlc L17-24Mar2011

BJT boundary and injection cond (npn) ©rlc L17-24Mar2011

BJT boundary and injection cond (npn) ©rlc L17-24Mar2011

IC npn BJT (*Fig 9.2a) ©rlc L17-24Mar2011

References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986. ©rlc L17-24Mar2011

References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986. ©rlc L17-24Mar2011