Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ Semiconductor Device Modeling and Characterization – EE5342 Lecture 35 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

Flat-band parameters for p-channel (n-subst) ©rlc L35-29Apr2011

Fully biased p- channel VT calc ©rlc L35-29Apr2011

p-channel VT for VC = VB = 0 Fig 10.21* ©rlc L35-29Apr2011

Ion implantation ©rlc L35-29Apr2011

“Dotted box” approx ©rlc L35-29Apr2011

©rlc L35-29Apr2011

Mobilities ©rlc L35-29Apr2011

Differential charges for low and high freq From Fig 10.27* ©rlc L35-29Apr2011

Ideal low-freq C-V relationship Fig 10.25* ©rlc L35-29Apr2011

Comparison of low and high freq C-V Fig 10.28* ©rlc L35-29Apr2011

Effect of Q’ss on the C-V relationship Fig 10.29* ©rlc L35-29Apr2011

n-channel enhancement MOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- n+ Depl Reg p-substrate Acceptors VB < 0 ©rlc L35-29Apr2011

Conductance of inverted channel Q’n = - C’Ox(VGC-VT) n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) The conductivity sn = (n’s/t) q mn G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’sqmnW) ©rlc L35-29Apr2011

Basic I-V relation for MOS channel ©rlc L35-29Apr2011

I-V relation for n-MOS (ohmic reg) ID non-physical ID,sat saturated VDS,sat VDS ©rlc L35-29Apr2011

Universal drain characteristic ID VGS=VT+3V 9ID1 ohmic saturated, VDS>VGS-VT VGS=VT+2V 4ID1 VGS=VT+1V ID1 VDS ©rlc L35-29Apr2011

Characterizing the n-ch MOSFET VD ID D G S B VT VGS ©rlc L35-29Apr2011

Low field ohmic characteristics ©rlc L35-29Apr2011

MOSFET Device Structre Fig. 4-1, M&A* ©rlc L35-29Apr2011

4-7a (A&M) ©rlc L35-29Apr2011

Figure 4-7b (A&M) ©rlc L35-29Apr2011

Figure 4-8a (A&M) ©rlc L35-29Apr2011

Figure 4-8b (A&M) ©rlc L35-29Apr2011

Body effect data Fig 9.9** ©rlc L35-29Apr2011

MOSFET equivalent circuit elements Fig 10.51* ©rlc L35-29Apr2011

n-channel enh. circuit model G RG Cgd RDS Cgs S RD D Cbd RB Cbs Idrain Cgb DSS DSD RB B ©rlc L35-29Apr2011

MOS small-signal equivalent circuit Fig 10.52* ©rlc L35-29Apr2011

MOSFET circuit parameters ©rlc L35-29Apr2011

MOSFET circuit parameters (cont) ©rlc L35-29Apr2011

Substrate bias effect on VT (body-effect) ©rlc L35-29Apr2011

Body effect data Fig 9.9** ©rlc L35-29Apr2011

Fully biased n- channel VT calc ©rlc L35-29Apr2011

Values for fms with silicon gate ©rlc L35-29Apr2011

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** |Q’d,max|/q (cm-2) xd,max (microns) ©rlc L35-29Apr2011

I-V relation for n-MOS ohmic ID non-physical ID,sat saturated VDS,sat ©rlc L35-29Apr2011

MOS channel- length modulation Fig 11.5* ©rlc L35-29Apr2011

Analysis of channel length modulation ©rlc L35-29Apr2011

References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997 ©rlc L35-29Apr2011