CS703 - Advanced Operating Systems By Mr. Farhan Zaidi

Lecture No. 28

Page Fault Frequency (PFF) PFF is a variable-space algorithm that uses a more ad hoc approach Attempt to equalize the fault rate among all processes, and to have a “tolerable” system-wide fault rate monitor the fault rate for each process if fault rate is above a given threshold, give it more memory so that it faults less if the fault rate is below threshold, take away memory should fault more, allowing someone else to fault less

Fault resumption. lets us lie about many things Emulate reference bits: Set page permissions to “invalid”. On any access will get a fault: Mark as referenced Emulate non-existent instructions: Give inst an illegal opcode. When executed will cause “illegal instruction” fault. Handler checks opcode: if for fake inst, do, otherwise kill. Run OS on top of another OS! Make OS into normal process When it does something “privileged” the real OS will get woken up with a fault. linux linux win98 linux privileged

external system bus (e.g. PCI) 32 bit address space 4 KB page size L1, L2, and TLBs 4-way set associative inst TLB 32 entries 8 sets data TLB 64 entries 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB -- 2 MB P6 Memory System DRAM external system bus (e.g. PCI) L2 cache cache bus bus interface unit inst TLB data TLB instruction fetch unit L1 i-cache L1 d-cache processor package

P6 2-level Page Table Structure Page directory 1024 4-byte page directory entries (PDEs) that point to page tables Page tables: 1024 4-byte page table entries (PTEs) that point to pages. Up to 1024 page tables 1024 PTEs page directory ... 1024 PDEs 1024 PTEs ... 1024 PTEs

Translating with the P6 TLB 1. Partition VPN into TLBT and TLBI. 2. Is the PTE for VPN cached in set TLBI? 3. Yes: then build physical address. 4. No: then read PTE (and PDE if not cached) from memory and build physical address. CPU virtual address 20 12 VPN VPO 16 4 TLBT TLBI 1 2 TLB hit TLB miss PDE PTE 3 ... 20 12 PPN PPO physical address page table translation 4