Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high duration; the low duration is defined similarly. The cycle time of a clock is the sum of its high duration and its low duration. The frequency of the clock is the reciprocal of the cycle time. high low time rising edge falling edge Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

State Elements A state element is a circuit component that is capable of storing a value. At the moment, we are interested primarily in state elements that store logical state information about the system, rather than data storage. A state element may be either unclocked or clocked. Clocked state elements are used in synchronous logic - When should an element that contains state be updated? - Edge-triggered clocking means that the state changes either on the rising or the falling edge. - Clock edge acts as a sampling signal that triggers the update of a state element. A signal that is to be written into a state element must be stable; i.e., it must be unchanging. If a function is to be computed in one clock cycle, then the clock period must be long enough to allow all the relevant signals to become stable. Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

An Unclocked State Element The set-reset (SR) latch - output depends on present inputs and also on past inputs Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Latches and Flip-flops Output is equal to the “stored value” inside the element Assume clocked state elements are used: latch: state changes whenever the inputs change, and the clock is asserted flip-flop: state changes only on a clock edge "logically true", — could mean electrically low A clocking methodology defines when signals can be read and written — wouldn't want to read a signal at the same time it was being written Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Clocked D-latch Two inputs: Two outputs: - the data value to be stored (D) - the clock signal indicating when to read and store D Two outputs: - the value of the internal state (Q) and its complement Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Clocked D Flip-flop Here’s a schematic for a D flip-flop with a falling edge trigger: Here’s a timing diagram illustrating the behavior of the circuit above: Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Our Implementation An edge triggered methodology Typical execution: - read contents of some state elements, - send values through some combinational logic - write results to one or more state elements Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

4-Bit Register Built using D flip-flops: Clock input controls when input is "written" to the individual flip-flops. However, the design above isn’t quite what we want… QTP What’s wrong with this? How can we fix it? Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens