Chapter 6 (I) CMOS Layout of Complexe Gate Designing Combinational Logic Circuits March 28, 2003

Example Gate: NAND

Example Gate: NOR

Complex CMOS Gate B C A D OUT = D + A • (B + C) A D B C Shown synthesis of pull up from pull down structure D B C

Constructing a Complex Gate OUT = D + A • (B + C)

Stick Diagrams Contains no dimensions Represents relative positions of transistors V DD V DD Inverter NAND2 Out Out In A B GND GND

Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B X = C • (A + B) C i Systematic approach to derive order of input signal wires so gate can be laid out to minimize area Note PUN and PDN are duals (parallel <-> series) Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions A B C A B PUN: Pull-up Network, PDN: Pull-down Network

Two Versions of C • (A + B) X C A B VDD GND Line of diffusion layout – abutting source-drain connections Note crossover eliminated by A B C ordering Two Strips Line of Diffusions One Strip Line of Diffusions

Consistent Euler Path (Insert D of textbook) VDD X B A j A path through all nodes in the graph such that each edge is visited once and only once. The sequence of signals on the path is the signal ordering for the inputs. PUN and PDN Euler paths are (must be) consistent (same sequence) If you can define a Euler path then you can generate a layout with no diffusion breaks A B C C A B B C A  no PDN B A C A C B -> no PDN C B A A B C GND

OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D

Example: x = ab+cd Euler Paths For both PUD and PDN

Cell Design Standard Cells (gate collection) Datapath Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width

Standard Cell Layout Methodology – 1980s VDD Routing channel VDD signals Contacts and wells not shown. What does this implement?? GND

Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 Contacts and wells not shown. What does this implement?? M3 GND GND Mirrored Cell

Standard Cells Cell height 12 metal tracks N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” V DD Out In 2 Rails ~10 GND Cell boundary

Standard Cells With minimal diffusion routing With silicided diffusion V DD With silicided diffusion V DD Out In Out In GND GND

Standard Cells 2-input NAND gate V DD A B Out GND