Beyond Si MOSFETs Part 1

Downscaling MOSFETs Downscaling leads to : increased leakage currents : decreased gate control : increase the electric field strength across the gate oxide. : randomness of dopant distribution Purpose of downscaling: To improve its performance for device applications. Consequence of downscaling : Power consumption is increasing and fabrication technology becomes increasingly complex. : when the gate oxide thickness is reduced, the gate leakage current will increase.

Physical Limits in Scaling Si MOSFET Gate stack Tunneling current ⇒ ⇑ Ioff Gate depletion ⇒ ⇑ EOT Power ⇑ CV2f ⇑ S/D leakage current ⇑ Gate leakage current ⇑ Source/Drain • Parasitic resistance • Doping level, abruptness Channel/Drain Surface scattering - mobility ⇓ High E-field - mobility ⇓ DIBL ⇒ drain to source leakage ⇑ Ioff Subthreshold slope ≥ kT/q ⇒ ⇑ Ioff VG – VT decrease ⇒ ⇓ ION Net result: Bulk-Si CMOS device performance increase commensurate with size scaling is unlikely beyond the 65 nm node

Factor That Effect Downscaling: Materials use a material with a higher dielectric constant, which increased the capacitance GaAs rather than Si: high electron mobility III-V heterojunction: higher electron mobility Ge and Si/SiGe heterojunctions: higher electron and hole mobility Use of SOI rather than bulk material: reduce capacitances and bulk effect Gating Schottky rather than oxide gate Multiple gating rather than single gate. (double gate has better electrostatic control of the channel compared to single gate, thus it reduced short channel effects) High mobility channel Geometry Vertical FETs rather than in-plane FETs Eg: novel SGFET from IC research

Effect of density of States High electron mobility in III-V semiconductor is primarily due to low effective mass. Which gives rise to low density of states. Which negatively impacts the drive current. The challenge for III-V CMOS: P-Channel (low hole mobility)

Materials Gating Use a material with a higher dielectric constant, which increased the capacitance. GaAs rather than Si; high electron mobility. Schottky rather than oxide gate. Used high gate dielectric thickness to reduce gate leakage.

Why GaAs Semiconductor EG (eV) ɛf Electron Mobility (cm2/V-sec) Hole Mobility (cm2/V-sec) Peak Electron Velocity (cm/sec) Si (bulk) 1.12 11.7 1,450 450 N.A. Ge 0.66 15.8 3,900 1,900 InP 1.35D 12.4 4,600 150 2.1 x 107 GaAs 1.42D 13.1 8,500 400 2 x 107 Ga0.47In0.53As 0.78D 13.9 11,000 200 2.7 x 107 InAs 0.35D 14.6 22,600 460 4 x 107 Al0.3Ga0.7As 1.80D 12.2 1,000 100 - AlAs 2.17 10.1 280 Al0.46In0.52As 1.92D 12.3 800

Why using Germanium MOS Transistor? Electronic Properties: More symmetric and higher carrier mobilities. ⇒ More efficient source injection ⇒ ↓ CMOS gate delay Smaller energy bandgap ⇒ Survives VDD scaling ⇒ ↓ R with ↓ barrier height Lower temperature processing ⇒ 3-D compatible

Gating Methods pn-junctions Schottky gate

Possible advantages of Schottky S/D MOSFET: • Better utilization of the metal/semiconductor interface Possible option to overcome the higher parasitic resistance • Modulation of the source barrier by the gate High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑ Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ Ioff ⇓ • Better immunity from short channel effects Possible Disadvantage • ION reduction due to the Schottky barrier

Gating: control of depletion

Schottky contact- re-visited

Work function Work function, qΦ Photoelectric effect Implication The energy, qΦ represents the minimum energy required for an electron to escape the material into vacuum. Photoelectric effect Implication

4. Energy band diagram: Vext = 0V Workfunction Φm < Φs Semiconductor type n-type e- transfer e- injection into metal more p-type near junction shortage of electrons. Ec bends away from EFs

Formation of Schottly Barrier Φm > Φs

5. Energy band diagram: Vext ≠ 0V

Built-in voltage in Schottky contact

Built-in voltage in Schottky contact

Ohmic contact (for camparison) Φm < Φs Small barrier opposing reverse flow from metal to semiconductor. Heavily doped semiconductor

Problem with Schottky barriers Simplified energy band diagram of metal-semiconductor interface that forms a Schottky barrier – ideal case

What happens with the semiconducting material at the metal-semiconductor interface? Interface seldom atomically sharp Incomplete covalent bond at interface For Si there exists always a thin oxide layer Barrier tends to be lower than predicted by metal and semiconductor bulk characteristics. No covalent bonding available at the surface Will try to trap charge from passing charged carriers or from carriers available in the surrounding atmosphere. The energy of these surface states is continuously distributed within the band gap of the semiconductor.

Interface states Interface states are characterized by a neutral level Φo such that the states below Φo are neutral when filled with electrons and above when empty.

Interface states More higher energetic electrons available in semiconductor and in interface layer -> charge re- distribution : e- from semiconductor into interface layer. But due to charge re-distribution (e.g. alignment of Fermi levels) Φo and EF have to align!! -> bandbending induced by surface states

Interface states