Hangzhou Dianzi University An Analysis of DG SOI MOSFET Modeling and Simulation with PSP, BSIM-IMG and HiSIM_SOTB Guofang Wang, Jun Liu June 21, 2019 The Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University

Outline 1、Introduction 2、Model Development 3、Model Verification 4、Conclusion Next, I will follow these four parts to give the presentation.

1. Introduction SOI (Silicon On Insulator) Bulk CMOS PD/FD SOI MOS Compared with bulk COMS, the SOI achieves excellent dielectric isolation, eliminating the inherent Latch-up effect of bulk silicon CMOS circuits, while having the advantages of small parasitic capacitance, high integration, and low leakage current. The SOI is generally classified into fully depleted FD structure and partially depleted PD structure according to the state of charge in the body region. The FD structure has a thin film , so when the device works, the depletion layer under the channel can fill the whole silicon thin film layer. In this way, floating body effect on partially depleted SOI can be eliminated. while the PD structure has a thick film. Therefore only part of the silicon layer under the channel is occupied by the depletion layer, resulting in charge accumulation in the electrically neutral region under the depletion layer, and causing floating body effect. this paper is based on partially depleted double-gate device. Bulk CMOS PD/FD SOI MOS

1. Introduction size of the device  reduced integration degree  increased application frequency  increased Undesirable phenomena  brought So, how did DG structure come? Well, In recent years, with the rapid development of CMOS process technology, the size of the device has been reduced , the integration degree and the application frequency have been increased. Some undesirable phenomena have been brought, too. Conventional planar single-gate (SG) structures can no longer meet the physical limit requirements imposed by device structures or material。 In order to meet this series of needs and suppress short channel effects (SCEs), a new structure called double-gate (DG) MOSFET was proposed

1. Introduction Advantages higher integration higher transconductance higher electron mobility inhibit SCEs Here, we give the schematic structure of DG MOSFET. L is the channel length, Tsi is the channel thickness, Tox1 is the thickness of the front gate oxide layer, and Tox2 is the thickness of the back-gate oxide layer. What are the advantages of double-gate structure compared with Conventional planar single-gate (SG) structure? Well, the double-gate structure has high transconductance, high electron mobility. The double-gate structure has a higher integration per unit area without affecting the good electrical characteristics of the devices, and they can effectively inhibit short channel effects (SCEs), because the back gate can efficacious block the field penetration from the drain. In this paper, PSP, BSIM-IMG, HiSIM_SOTB are selected to modeling and simulation based on a 130-nm(nano-meters) DG SOI MOSFET transistor. schematic structure of DG MOSFET

2. Model Development and Extraction PSP physical equations and scalability contain all physical effects substrate model As everyone knows, PSP is jointly developed by NXP Semiconductors and France’s CEA-LETI. PSP is the merger of MOS Model 11 (Philips) and SP (the Pennsylvania State University) PSP is based on physical equations and scalability. It contains all relational physical effects, such as mobility reduction, velocity saturation, DIBL, STI stress, etc. But the substrate model is not detailed enough. PSP NXP CEA-LETI

2. Model Development and Extraction BSIM-IMG Advantages: independent double-gate structure FD & DG devices back gate biasing effect back-gate depletion Disadvantages: no charge accumulation Process affect switch application BSIM-IMG is developed by UC Berkeley and characterizes the double gate device in advanced process nodes. This model has a separate double gate structure, namely the front gate and the back gate. BSIM-IMG has different work functions and different dielectric thicknesses. It is suitable for fully depleted devices and DG devices. The BSIM-IMG model includes back-gate-related effects, such as back gate biasing effect and back-gate depletion. The back-gate bias is added to give a better control of the threshold voltage in BSIM-IMG. The threshold voltage can be given as the expression. But it has no charge accumulation process causing cgg cannot be fitted in the negative gate voltage region, or affecting the switch application;  

2. Model Development and Extraction HiSIM_SOTB Advantages: ultra-thin SOI BOX layer double-gate structure all the charges Disadvantages: model description substrate model HiSIM_SOTB is developed by Hiroshima University and it is a descendant of HiSIM_SOI valid for ultra-thin SOI and BOX layers applicable even for the double-gate structure as a specific structure of SOTB-MOSFET. The model considers all the charges that may be generated in the device. The surface-potential-based model requires no threshold voltage in its core description of the model. However, HiSIM_SOTB has opted for modeling various submodels such as short-channel effects as a threshold voltage shift from an otherwise ideal case. The whole contribution to the threshold voltage is summarized as the expression. But the model description and substrate model is not detailed enough.  

3、Model Verification HiSIM_SOTB BSIM-IMG & PSP   Next is model verification. Here, the C-V data is fitted to extract parameters that affect the DC characteristic of MOSFEET, such as the thickness of the front gate oxide, the doping concentration of the substrate. a large-sized MOSFET device is selected for gate capacitance testing to reduce the effect of parasitic capacitance on the measurement results. The gate capacitance is the sum of cgs, cgd and cgb, It is clearly that HiSIM_SOTB is the best fitting for gate capacitance . HiSIM_SOTB BSIM-IMG & PSP  

the two simulation lines are almost coincident 3、Model Verification PSP IN next figures, the measurement (dots) and simulation (lines) with PSP, HiSIM_SOTB and BSIM-IMG are shown at fixed drain source voltage and Vbg = -5 V, 0 V, 5 V, where transfer characteristic and transconductance are shown in (a) and (b), respectively. From this figure the two simulation lines are almost coincident using PSP model at Vbg = -5 V and 0 V. (b)transconductance transfer characteristic the two simulation lines are almost coincident at Vbg = - 5 V and Vbg = 0 V

3、Model Verification BSIM-IMG (b)transconductance In this figure, it is clearly shows that the simulation date with BSIM-IMG model can fit the curves well in different back-gate bias. transfer characteristic (b)transconductance The three simulation lines are fitting good at different back-gate bias

the two simulation lines are almost coincident 3、Model Verification HiSIM_SOTB As can be seen from the figure , there are two simulation lines with HiSIM_SOTB model at Vbg = 0 V and 5 V. They are almost coincident, somewhat similar to the PSP model. transfer characteristic (b)transconductance the two simulation lines are almost coincident at Vbg = 0 V and Vbg = 5 V

Comparison of transfer characteristics at Vbg = -5 V 3、Model Verification The figure shows the comparison of transfer characteristics of DG MOSFET transistor versus front-gate voltage (Vfg) with PSP, HiSIM-SOTB and BSIM-IMG models at the back-gate voltage is - 5 V(volt) Comparison of transfer characteristics at Vbg = -5 V

Comparison of transfer characteristics at Vbg = 0 V 3、Model Verification In this figure the back-gate voltage is 0 V(volt) Comparison of transfer characteristics at Vbg = 0 V

Comparison of transfer characteristics at Vbg = 5 V 3、Model Verification In the figure the back-gate bias is 5 V(volt) Comparison of transfer characteristics at Vbg = 5 V

3、Model Verification Table Error of simulation accuracy Model Error at Vbg = - 5 V Error at Vbg = 0 V Error at Vbg = 5 V PSP 12.70% 14.90% 6.72% HiSIM_SOTB 19.82% 14.89% 13.37% BSIM-IMG 11.47% 7.57% 6.10% In order to further verify, the error analysis of simulation accuracy with PSP, HiSIM_SOTB and BSIM-IMG for Drain source voltage is 100 mV(millivolt), 525 mV(millivolt), 1.8 V(volt), at the back-gtae bias is - 5 V(volt), 0 V(volt), 5 V(volt), , respectively. It is obviously that the simulation accuracy of BSIM-IMG model is the best than the other models. Compared with PSP, the average simulation accuracy of BSIM-IMG is improved by ~3%(percent), while compared with HiSIM-SOTB, the average accuracy is improved by ~7.7%.(percent)

4. Conclusion Three models are selected to modeling and simulation C-V and I-V characteristics have been presented The BSIM-IMG model has slightly insufficient in C-V characteristic BSIM-IMG is more accurate in I-V characteristic In this paper, three models are selected to modeling and simulation based on a 130-nm(nano-meters) DG(double-gate) SOI MOSFET transistor. And the paper has presented that the extraction and comparison of C-V and I-V characteristics with PSP, BSIM-IMG and HiSIM_SOTB. Due to BSIM-IMG model is a fully depleted device with no charge accumulation process, it has slightly insufficient in C-V characteristic. But BSIM-IMG is more accurate than PSP and HiSIM_SOTB for double-gate SOI MOSFET in I-V characteristic, especially when changing with the back-gate voltage.

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