Design Principles of Scalable Switching Networks

Slides:



Advertisements
Similar presentations
Switching - Fabric An Engineering Approach to Computer Networking.
Advertisements

Optimization Problems in Optical Networks. Wavelength Division Multiplexing (WDM) Directed: Symmetric: Undirected: Optic Fiber.
Midwestern State University Department of Computer Science Dr. Ranette Halverson CMPS 2433 – CHAPTER 4 GRAPHS 1.
Chapter 9 Graph algorithms. Sample Graph Problems Path problems. Connectedness problems. Spanning tree problems.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scaling.
MAE 552 – Heuristic Optimization Lecture 26 April 1, 2002 Topic:Branch and Bound.
CSE 291-a Interconnection Networks Lecture 7: February 7, 2007 Prof. Chung-Kuan Cheng CSE Dept, UC San Diego Winter 2007 Transcribed by Thomas Weng.
Interconnection Networks in Multiprocessor Systems By: Wallun Chan Course: CS 147 Text: Chapter 12, p Professor: Sin-Min Lee.
1 Dynamic Interconnection Networks Miodrag Bolic.
EE384y EE384Y: Packet Switch Architectures Part II Scaling Crossbar Switches Nick McKeown Professor of Electrical Engineering and Computer Science,
Shanghai Jiao Tong University 2012 Indirect Networks or Dynamic Networks Guihai Chen …with major presentation contribution from José Flich, UPV (and Cell.
1 Multicasting in a Class of Multicast-Capable WDM Networks From: Y. Wang and Y. Yang, Journal of Lightwave Technology, vol. 20, No. 3, Mar From:
Data Structures & Algorithms Graphs
Birds Eye View of Interconnection Networks
Circuit Switching Circuit switching networks,
Interconnect Networks Basics. Generic parallel/distributed system architecture On-chip interconnects (manycore processor) Off-chip interconnects (clusters.
Based on An Engineering Approach to Computer Networking/ Keshav
Proof of correctness of Dijkstra’s algorithm: Basically, we need to prove two claims. (1)Let S be the set of vertices for which the shortest path from.
Data Structures and Algorithm Analysis Lecture 5
INTERCONNECTION NETWORK
Hamiltonian Graphs Graphs Hubert Chan (Chapter 9.5)
The NP class. NP-completeness
EE384Y: Packet Switch Architectures Scaling Crossbar Switches
Overview Parallel Processing Pipelining
Network Resources.
Copyright © Zeph Grunschlag,
Auburn University COMP8330/7330/7336 Advanced Parallel and Distributed Computing Interconnection Networks (Part 2) Dr.
Chapter 8 Switching Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Dynamic connection system
Bipartite Matching Lecture 8: Oct 7.
URL: Chapter 8 Switching Tel: (03) Ext: URL:
The minimum cost flow problem
Lecture 2. Switching of physical circuits.
Refer example 2.4on page 64 ACA(Kai Hwang) And refer another ppt attached for static scheduling example.
Euler Paths and Circuits
Applied Combinatorics, 4th Ed. Alan Tucker
Hamiltonian Graphs Graphs Hubert Chan (Chapter 9.5)
Algorithms and Networks
Algorithm Design and Analysis
Lectures on Network Flows
Basics of Digital Logic Design Presentation D
Great Theoretical Ideas in Computer Science
Packet Switching (basics)
Chapter 5. Optimal Matchings
Chapter 7 Network Flow Slides by Kevin Wayne. Copyright © 2005 Pearson-Addison Wesley. All rights reserved.
Multiprocessors Interconnection Networks
Discrete Mathematics for Computer Science
The Art Gallery Problem
Multi-Way Search Trees
Instructor: Shengyu Zhang
Indirect Networks or Dynamic Networks
3.5 Minimum Cuts in Undirected Graphs
Lectures on Graph Algorithms: searching, testing and sorting
3.4 Push-Relabel(Preflow-Push) Maximum Flow Alg.
High Performance Computing & Bioinformatics Part 2 Dr. Imad Mahgoub
Applied Combinatorics, 4th Ed. Alan Tucker
Applied Combinatorics, 4th Ed. Alan Tucker
CSE 421: Introduction to Algorithms
Data Communications and Networking
Branch and Bound Searching Strategies
Dynamic Interconnection Networks
Topic 5: Heap data structure heap sort Priority queue
Flow Feasibility Problems
Trevor Brown DC 2338, Office hour M3-4pm
Dynamic Programming II DP over Intervals
Directional consistency Chapter 4
Error Correction Coding
Chapter 9 Graph algorithms
Prof. Ramin Zabih Graph Traversal Prof. Ramin Zabih
Circuit Switch Design Principles
Presentation transcript:

Design Principles of Scalable Switching Networks Shanghai Jiao Tong University Design Principles of Scalable Switching Networks

2×2 Switching Network Most simplest switching network Bar State Cross State

𝑁×𝑁 Switching Network 1 ? 1 2 2 3 3 4 4

𝑁×𝑁 Crossbar Implement an 𝑁×𝑁 switch by an array of 2×2 switches Connection from input 𝑖 to output 𝑗 Set the switch 𝑖,𝑗 to the bar state Set other switches along the path to the cross state 1 1 2 2 3 3 4 4

A new Connection New connections between a pair of free input and output can be freely set up without distribution of existing connections 1 1 2 2 3 3 4 4

Strictly Non-Blocking (SNB) A switch is SNB if a connection can always be set up between any idle (or free) input and output without the need to rearrange the paths of the existing connections

Performance of 𝑁×𝑁 Crossbar Crossbar Implementation: SNB Routing complexity: 𝑂 1 Hardware complexity: 𝑂 𝑁 2 1 1 2 2 3 3 4 4

Lower Bound of Hardware Requirement An 𝑁×𝑁 switch can support 𝑁! mappings Let 𝑀 be the minimal number of required crosspoints # states ≥ # mappings 2 𝑀 ≥𝑁! 𝑀≥ log 2 𝑁! ≈𝑁 log 2 𝑁 for large 𝑁 How to reach this lower bound? 1 2 N .

Scalable Design: Two-Stage Network Blocking Input 2 cannot be connected to output 2 if input 1 is already connected to output 1 1 2 3 4

Scalable Design: Dilated Two-Stage Network There are multiple links between the modules at two adjacent stages 1 2 3 4

Performance of Dilated Networks Suppose 𝑁=𝑟𝑛 Bandwidth expansion factor = 𝑛: nonblocking Number of crosspoints: 𝑛×𝑟𝑛 ×2𝑟=2 𝑁 2 =𝑂 𝑁 2 1 2 r . n n 虽然不是低复杂度的设计,但是提供了一个很好的信息:要想无阻塞,在每对输入输出模块之间至少要有n条路

Scalable Design: Three-Stage Network Clos Network by C. Clos in 1953 𝑛 1 𝑟 1 = 𝑛 3 𝑟 3 = 𝑁 for 𝑁×𝑁 switch There is exactly one link between the modules at two adjacent stages n1 × r2 r1 × r3 r2 × n3 (1) (2) (r1) (r2) (r3) Input Stage Central Stage Output Stage

Routing Constraint Contention-free routing condition: Two connections from the same input module (or to the same output module) can not share the same central module A F G B 1 2 3 4 5 6 7 8 9 H 虽然clos网络也可以实现无阻塞,但是也不是没有前提的。

Condition on 𝑟 2 𝑟 2 central modules provide 𝑟 2 paths for each pair of input module and output module It seems that 𝑟 2 should be larger than 𝑛 1 and 𝑛 3 Is this condition enough? A F G B 1 2 3 4 5 6 7 8 9 H

Example A request for connection from input 9 to output 4 is blocked 𝑆 3 ≜ set of central modules used by input module 3 = 𝐹,𝐺 𝐷 2 ≜ set of central modules used by output module 2 = 𝐻 Hint: find an central module that is not used by both the input module and the output module A F G B 1 2 3 4 5 6 7 8 9 H

One Possible Solution Increase the number of central modules

One Possible Solution Such that a new path always available for new connection

SNB iff 𝑟 2 ≥ min 𝑛 1 + 𝑛 3 −1,𝑁 Proof: 1) Trivial case: 𝑁≤ 𝑛 1 + 𝑛 3 −1 2) If 𝑁> 𝑛 1 + 𝑛 3 −1, consider the worst case where all other inputs in input module 𝑖 and all other outputs in output module 𝑗 are busy, i.e., 𝑆 𝑖 = 𝑛 1 −1, 𝐷 𝑗 = 𝑛 3 −1. It follows that 𝑆 𝑖 ∪ 𝐷 𝑗 = 𝑆 𝑖 + 𝐷 𝑗 − 𝑆 𝑖 ∩ 𝐷 𝑗 ≤ 𝑆 𝑖 + 𝐷 𝑗 = 𝑛 1 + 𝑛 3 −2. Thus, if 𝑟 2 ≥ 𝑛 1 + 𝑛 3 −1, there is at least one central module available for the request from input module 𝑖 to output module 𝑗 if there is a new request from 𝑖 to 𝑗

Hardware Complexity of SNB Clos Networks Suppose 𝑟 1 = 𝑛 1 = 𝑟 3 = 𝑛 3 = 𝑁 . To be SNB, 𝑟 2 ≥ 𝑛 1 + 𝑛 3 −1=2 𝑁 −1. In this case, the number of needed crosspoints is 2 𝑁 × 𝑁 × 𝑁 + 2 𝑁 −1 × 𝑁 × 𝑁 =4 𝑁 3 2 −𝑁

Comments on SNB Clos Networks The hardware complexity of an 𝑁×𝑁 SNB Clos network is less than that of an 𝑁×𝑁 crossbar when 𝑁>14 However, the routing process in the SNB Clos network is more complex than the crossbar Can the hardware complexity of Clos networks be further reduced?

Another Possible Approach If a new connection request is blocked, it can still be satisified if we rearrange some exsiting connections 4 1 2 3 4 1 2 3

Rearrangeably Non-Blocking (RNB) A switch is rearrangeably non-blocking if a connection can always be set up between any idle input and output, although it may be necessary to rearrange the existing connections

Paull Matrix Row 𝑖: input module 𝑖 Column 𝑗: output module 𝑗 Entry 𝑖,𝑗 : set of central modules used by the connections from input module 𝑖 to output module 𝑗 F,G,H 2 1 i r1 j r2 Output Module Input Module i j F G H 为了更好地观察这种路由限制,定义Paull矩阵

A Legitimate Paull Matrix In row 𝑖: 𝑆 𝑖 is the set of central modules appear in row 𝑖 A central module appears in row 𝑖 or 𝑆 𝑖 only once Number of employed modules: 𝑆 𝑖 ≤min 𝑛 1 , 𝑟 2 In column 𝑗: 𝐷 𝑖 is the set of central modules appear in column 𝑗 A central module appears in column 𝑗 or 𝐷 𝑗 only once Number of employed modules: 𝐷 𝑗 ≤min 𝑛 3 , 𝑟 2

Example: Blocking Let 𝑀= 𝐴,𝐵,𝐶 be the set of central modules 𝑆 2 = 𝐴,𝐵 𝐷 3 = 𝐴,𝐶 Request 6->9, input 6 is an input of input module 2 and output 9 is an output of output module 3, can not be built up since 𝑀− 𝑆 2 ∪ 𝐷 3 =𝜙 B 2 1 3 C A 4

Example: Alternating Chain 𝑆 2 does not contain 𝐵, and 𝐷 3 does not have 𝐶: find C-B chain B 2 1 3 C A 4 C 2 1 3 B A 4

Example: Setup New Connection 𝑆 2 and 𝐷 3 do not have 𝐶: assign 𝐶 to the new connection C 2 1 3 B A,C 4 A

RNB iff 𝑟 2 ≥ min 𝑛 1 , 𝑛 3 Proof: 1) Only if: trivial 2) if: similarly, we consider the worst case, where where all other inputs in input module 𝑖 and all other outputs in output module 𝑗 are busy, i.e., 𝑆 𝑖 = 𝑛 1 −1, 𝐷 𝑗 = 𝑛 3 −1. Thus, there are two cases: a) 𝑆 𝑖 ∪ 𝐷 𝑗 < 𝑟 2 , and b) 𝑆 𝑖 ∪ 𝐷 𝑗 = 𝑟 2 . As to case (1), a new connection from input module 𝑖 to output module 𝑗 can be immediately set up. For case (2), we have 𝑆 𝑖 − 𝐷 𝑗 = 𝑆 𝑖 ∪ 𝐷 𝑗 − 𝐷 𝑗 ≥ 𝑟 2 − 𝑛 3 −1 ≥ 𝑛 3 − 𝑛 3 +1=1, and 𝐷 𝑗 − 𝑆 𝑖 = 𝑆 𝑖 ∪ 𝐷 𝑗 − 𝑆 𝑖 ≥ 𝑟 2 − 𝑛 1 −1 ≥ 𝑛 1 − 𝑛 1 +1=1. It follows that: ∃ a central module, say 𝐴, in 𝑆 𝑖 but not in 𝐷 𝑗 or

RNB iff 𝑟 2 ≥ min 𝑛 1 , 𝑛 3 (con’t) ∃ a central module, say 𝐵, in 𝐷 𝑗 but not in 𝑆 𝑖 . This is visualized as follows: A B 𝑖 ′ 𝑖 𝑗 ′ 𝑗 𝑖 ′′ 𝑖 ′′′ 𝑗 ′′ 𝑖 ′ 𝑖 ′′ 𝑖 𝑖 ′′′ . 𝑗 ′ 𝑗 𝑗 ′′ A B 𝑖 already connects to all middle-stage nodes except 𝐵 𝑗 already connects to all middle-stage nodes except 𝐴

RNB iff 𝑟 2 ≥ min 𝑛 1 , 𝑛 3 (con’t) We can obtain a new legitimate Paull matrix, by rearranging the Paull matrix as follows: A B 𝑖 ′ 𝑖 𝑗 ′ 𝑗 𝑖 ′′ 𝑖 ′′′ 𝑗 ′′ B . 𝑖 ′ 𝑖 ′′ 𝑖 𝑖 ′′′ . 𝑗 ′ 𝑗 𝑗 ′′ A B

Bipartite Model Input/output module ↔ a node in 𝑋/𝑌 Connection ↔ an edge Central module ↔ a color Routing constraints: two edges share the same node can not use the same color

Example: Alternating Path and Color Exchange

Hardware Complexity of SNB Clos Networks Suppose 𝑟 1 = 𝑛 1 = 𝑟 3 = 𝑛 3 = 𝑁 . To be RNB, 𝑟 2 ≥ max 𝑛 1 , 𝑛 3 = 𝑁 . In this case, the number of needed crosspoints is 2 𝑁 × 𝑁 × 𝑁 + 𝑁 × 𝑁 × 𝑁 =3 𝑁 3 2 Recall that, the number of crosspoints needed by an SNB network is 4 𝑁 3 2 −𝑁 Can the hardware complexity be further reduced?

Benes Network The 𝑁×𝑁 network is RNB if each 𝑁 2 × 𝑁 2 network are RNB 2 × 2 𝑁 2 × 𝑁 2 . 1 2 3 4 N-1 N

Recursive Decomposition A 16×16 Benes Network

Recursive Decomposition A 16×16 Benes Network

Recursive Decomposition A 16×16 Benes Network

Complexity Let 𝑁= 2 𝑛 and 𝑓 𝑘 be number of stages of a 𝑘×𝑘 Benes network. We have 𝑓 𝑁 =𝑓 𝑁 2 +2 then 𝑓 2 𝑛 =𝑓 2 𝑛−1 +2 =𝑓 2 𝑛−2 +2×2 =⋯ =𝑓 2 𝑛−𝑗 +2×𝑗 =⋯ =𝑓 2 +2 𝑛−1 =1+2 𝑛−1 =2𝑛−1=2 log 𝑁 −1 Thus, number of 2×2 switches is 𝑂 𝑁 log 𝑁

Loop Routing Algorithm: 𝑂 𝑁 log 𝑁 Set up paths for input-output pairs (1, 4), (2, 5), (3, 6), (4, 3) (5, 7), (6, 8), (7, 1), (8, 2) 1 2 3 4 5 6 7 8