Advanced Computer Architecture Lecture 23 Tree and hypercube interconnects Routers Lillevik 437s06-l23 University of Portland School of Engineering

No global or shared memory Distributed computer Interconnect P M ... No global or shared memory Lillevik 437s06-l23 University of Portland School of Engineering

Trees may have k nodes-per-branch Binary tree Binary tree: re-drawn Trees may have k nodes-per-branch Lillevik 437s06-l23 University of Portland School of Engineering

Find the following? Diameter: 2log2n Average distance: log2n Binary tree, n nodes Diameter: 2log2n Average distance: log2n Bisection BW: 1 Lillevik 437s06-l23 University of Portland School of Engineering

Cables problematic for large D Hypercube 4-D 2-D 0-D 1-D 3-D 5-D Cables problematic for large D Lillevik 437s06-l23 University of Portland School of Engineering

Hypercube, n nodes (n = 2D) Find the following? Hypercube, n nodes (n = 2D) Diameter: log2 n Average distance: log2 n Bisection BW: Lillevik 437s06-l23 University of Portland School of Engineering

Routing algorithms Route: path a message must traverse Node ID = (x, y, z, …) Algorithm Route x dimension, then y, etc.  in order Avoids deadlock, maximum utilization Lillevik 437s06-l23 University of Portland School of Engineering

Node (1,0) sends message to node (2,3) Mesh routing example (0,0) (3,0) (3,3) (0,3) Node (1,0) sends message to node (2,3) (1,0)  (2,0)  (2,1)  (2,2)  (2,3) x - dim y - dim Lillevik 437s06-l23 University of Portland School of Engineering

Node (1,0,0) sends message to node (0,1,1) Find routing path? (0,0,0) (1,0,0) (1,1,0) (0,1,1) (1,1,1) (0,0,1) Node (1,0,0) sends message to node (0,1,1) Lillevik 437s06-l23 University of Portland School of Engineering

Nodes connected by links Processor and Router link Node Processor Router Links Simple bus Protocol Lillevik 437s06-l23 University of Portland School of Engineering

Router connects processor to links Router interfaces Router  Processor Interface Link Interfaces Router connects processor to links Lillevik 437s06-l23 University of Portland School of Engineering

Processor interface signals? A, D, C buses Ack, clk, reset Breq, BGnt Ben Lillevik 437s06-l23 University of Portland School of Engineering

Link interface signals? Send, receive IRQ, INTA Ready Lillevik 437s06-l23 University of Portland School of Engineering

Unidirectional ring router Processor Ring router contains three ports Lillevik 437s06-l23 University of Portland School of Engineering

Unidirectional ring router signals IReq IAck In OReq OAck Out RReq WReq RAck WAck D Link input Link output Processor Lillevik 437s06-l23 University of Portland School of Engineering

Mesh router contains five ports North Router West East South Processor Mesh router contains five ports Lillevik 437s06-l23 University of Portland School of Engineering

Mesh router signals? ERReq, ERAck, ….. Lillevik 437s06-l23 University of Portland School of Engineering

Ring router block diagram In I/F Out I/F CPU I/F Latch Controller Driver Lillevik 437s06-l23 University of Portland School of Engineering

Ring router schematic Lillevik 437s06-l23 University of Portland School of Engineering

Ring router modes Pass Write: CPU writing to router (source) Message passing through router, independent of local CPU activity Source an upstream CPU, destination a downstream CPU Write: CPU writing to router (source) Read: CPU reading from router (destination) DMA Lillevik 437s06-l23 University of Portland School of Engineering

Interference Routers support multiple modes (pass, read, write, broadcast, etc.) Some modes independent and support concurrency (parallel) Some modes are exclusive (dependent) Requires arbitration to resolve Results in message blocking and network interference Lillevik 437s06-l23 University of Portland School of Engineering

Pass mode data flow Latch In Out In I/F Controller Out I/F CPU I/F Driver Lillevik 437s06-l23 University of Portland School of Engineering

Write mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F Driver Lillevik 437s06-l23 University of Portland School of Engineering

Read mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F Driver Lillevik 437s06-l23 University of Portland School of Engineering

Message format Header: routing and control information Payload: data Trailer: error checking code (ECC) time Trailer Payload Header Lillevik 437s06-l23 University of Portland School of Engineering

Eight-node example 4 6 1 3 7 5 2 Write Pass Read Lillevik 437s06-l23 4 6 1 3 7 5 2 Write Pass Read Lillevik 437s06-l23 University of Portland School of Engineering

Lillevik 437s06-l23 University of Portland School of Engineering

Find the following? Diameter: 2 log2 n Average distance: log2 n Binary tree, n nodes Diameter: 2 log2 n Average distance: log2 n Bisection BW: 1 Lillevik 437s06-l23 University of Portland School of Engineering

Hypercube, n nodes (n = 2D) Find the following? Hypercube, n nodes (n = 2D) Diameter: log2 n Average distance: 1/2 log2 n Bisection BW: Lillevik 437s06-l23 University of Portland School of Engineering

Node (1,0,0) sends message to node (0,1,1) Find routing path? (0,0,0) (1,0,0) (1,1,0) (0,1,1) (1,1,1) (0,0,1) Node (1,0,0) sends message to node (0,1,1) (1,0,0)  (0,0,0)  (0,1,0)  (0,1,1) Lillevik 437s06-l23 University of Portland School of Engineering

Processor interface signals? Processor output request Processor output acknowledge Processor input request Processor input acknowledge Lillevik 437s06-l23 University of Portland School of Engineering

Link interface signals? Link output request Link output acknowledge Link input request Link input acknowledge Lillevik 437s06-l23 University of Portland School of Engineering

Mesh router signals? PIReq, PIAck, POReq, POAck, PData NIReq, NIAck, NOReq, NOAck, NData EIReq, EIAck, EOReq, EOAck, EData SIReq, SIAck, SOReq, SOAck, SData WIReq, WIAck, WOReq, WOAck, WData Lillevik 437s06-l23 University of Portland School of Engineering

Write mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F Driver Lillevik 437s06-l23 University of Portland School of Engineering

Read mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F Driver Lillevik 437s06-l23 University of Portland School of Engineering