Advanced Computer Architecture Lecture 7 Bus analysis DC and AC Lillevik 437s06-l7 University of Portland School of Engineering

Project 2 team reviews Team Cat Team Dog Lillevik 437s06-l7 University of Portland School of Engineering

System view of a computer ··· Agent 0 Agent n ··· Signal 0 Signal n  Bus One agent at-a-time owns the bus Lillevik 437s06-l7 University of Portland School of Engineering

Bus analysis DC AC Checks static conditions Review high and low logic levels AC Checks dynamic conditions All flip-flops must meet setup and hold times Lillevik 437s06-l7 University of Portland School of Engineering

VH drops and VL increases with greater current DC analysis Driver outputs High: source current Low: sink current Receiver inputs High: sink current Low: source current VH drops and VL increases with greater current Lillevik 437s06-l7 University of Portland School of Engineering

Load current N Driver Receiver(s) High Low IOH IIH IOL IIL Lillevik 437s06-l7 University of Portland School of Engineering

Example assumptions Driver: 74LS240 Receivers: 74LS74 Lillevik 437s06-l7 University of Portland School of Engineering

Why does it sink so much current? 74LS240 data sheet Why does it sink so much current? Lillevik 437s06-l7 University of Portland School of Engineering

74LS74 data sheet Lillevik 437s06-l7 University of Portland School of Engineering

How many loads max? Lillevik 437s06-l7 University of Portland School of Engineering

Driving more loads Change/mix logic families, add logic conversion circuit Put drivers in parallel, separate traces Lillevik 437s06-l7 University of Portland School of Engineering

Bus timing (AC) analysis How fast can we go? Lillevik 437s06-l7 University of Portland School of Engineering

Problem statement Sum of all delays < clock cycle Delays: in addition to logic Clock skew (often largest) Input (setup, hold) Output (valid) Propagation delay (ps/inch) Margin (safety factor, 5-10%) Lillevik 437s06-l7 University of Portland School of Engineering

Clock skew The rising edge varies across topology Bus Signal Dev 1 Dev b Dev a Clk-dev 1 Clk-dev 2 Tskew The rising edge varies across topology Lillevik 437s06-l7 University of Portland School of Engineering

Input timing Setup is typically far more critical then hold Clk In Out Q Clk In Out Clk Tsetup Thold In Setup is typically far more critical then hold Lillevik 437s06-l7 University of Portland School of Engineering

Output timing It takes time for the output to change Clk In Out D Q Tvalid Out It takes time for the output to change Lillevik 437s06-l7 University of Portland School of Engineering

Propagation delay Bus Signal Dev 1 Dev 2 Dev b Dev a Driver Receiver Tprop Signal-dev 1 Signal-dev 2 Delay varies with the electrical properties of the media (pcb, package, sockets, vias, etc.) and trace length Lillevik 437s06-l7 University of Portland School of Engineering

Timing Analysis Clk In Out D Q Bus Signal Lillevik 437s06-l7 University of Portland School of Engineering

Example assumptions Trace impedance: 50Ω , single-ended, 1.25 ns/in Bus lengths: 3-10 inches Clock skew: 30 ns 74LS74 flip flops Margin of 10% Lillevik 437s06-l7 University of Portland School of Engineering

74LS74 data sheet Lillevik 437s06-l7 University of Portland School of Engineering

74LS74 data sheet, continued. Lillevik 437s06-l7 University of Portland School of Engineering

Find max clock frequency? Lillevik 437s06-l7 University of Portland School of Engineering

Another example Fmax = 10 MHz Trace impedance: 50Ω , single-ended, 1.25 ns/in Bus length: 5 inches 74LS74 flip flops Margin of 5% Lillevik 437s06-l7 University of Portland School of Engineering

Find maximum clock skew? Lillevik 437s06-l7 University of Portland School of Engineering

High-speed bus analysis Entire system modeled (IBIS) Silicon  package  traces/vias  package  silicon Electrical path a transmission line 3-D field solver (iterative) May take 24 -48 hours of simulation time Results in bus guideline document (sample design) Lillevik 437s06-l7 University of Portland School of Engineering

Example product sheet Lillevik 437s06-l7 University of Portland School of Engineering

Lillevik 437s06-l7 University of Portland School of Engineering

Max load (fan-out) of ~15 devices How many loads max? Max load (fan-out) of ~15 devices Lillevik 437s06-l7 University of Portland School of Engineering

Find max clock frequency? Lillevik 437s06-l7 University of Portland School of Engineering

Find maximum clock skew? Lillevik 437s06-l7 University of Portland School of Engineering