Lecture 1: Introduction

Courtesy Texas Instruments A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2010 Intel Core i7 mprocessor 2.3 billion transistors 64 Gb Flash memory > 16 billion transistors Courtesy Texas Instruments [Trinh09] © 2009 IEEE 1: Circuits & Layout

Growth Rate 53% compound annual growth rate over 50 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society [Moore65] Electronics Magazine 1: Circuits & Layout

Annual Sales >1019 transistors manufactured in 2008 1 billion for every human on the planet 1: Circuits & Layout

MOS Integrated Circuits 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power Intel Museum. Reprinted with permission. [Vadasz69] © 1969 IEEE. Intel 1101 256-bit SRAM Intel 4004 4-bit mProc 1: Circuits & Layout

Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates [Moore65] Electronics Magazine 1: Circuits & Layout

And Now… 1: Circuits & Layout

Feature Size Minimum feature size shrinking 30% every 2-3 years 1: Circuits & Layout

Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance 1: Circuits & Layout

Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip 0: Introduction

Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors 0: Introduction

Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) 0: Introduction

p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction 0: Introduction

nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is no longer made of metal* * Metal gates are returning today! 0: Introduction

nMOS Operation Body is usually tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF 0: Introduction

nMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON 0: Introduction

pMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior 0: Introduction

Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … 0: Introduction

Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain 0: Introduction

CMOS Inverter A Y 1 OFF ON 1 ON OFF 0: Introduction

CMOS NAND Gate A B Y 1 OFF ON 1 OFF ON 1 ON OFF ON OFF 1 1 OFF ON 1 OFF ON 1 ON OFF ON OFF 1 0: Introduction

CMOS NOR Gate A B Y 1 0: Introduction

3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 0: Introduction

Compound Gate 0: Introduction

Fig. 13. 16 Proper transistor sizing for a four-input NOR gate Fig. 13.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter. Microelectronic Circuits - Fourth Edition Sedra/Smith

Fig. 13. 17 Proper transistor sizing for a four-input NAND gate Fig. 13.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter. Microelectronic Circuits - Fourth Edition Sedra/Smith

Non-inverting Buffer

AND Gate

OR Gate

Inverter+NAND+NOR    

Inverter+NAND+NOR Design a CMOS digital circuit that realizes the Boolean function  

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process 0: Introduction

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors 0: Introduction

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps 0: Introduction

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line 0: Introduction

Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal 0: Introduction

Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted. 0: Introduction

Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 0: Introduction

Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace 0: Introduction

Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light 0: Introduction

Lithography Expose photoresist through n-well mask Strip off exposed photoresist 0: Introduction

Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed 0: Introduction

Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step 0: Introduction

n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si 0: Introduction

Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps 0: Introduction

Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor 0: Introduction

Polysilicon Patterning Use same lithography process to pattern polysilicon 0: Introduction

Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact 0: Introduction

N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing 0: Introduction

N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion 0: Introduction

N-diffusion cont. Strip off oxide to complete patterning step 0: Introduction

P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact 0: Introduction

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed 0: Introduction

Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires 0: Introduction

Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process 0: Introduction

Simplified Design Rules Conservative rules to get you started 0: Introduction

Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long 0: Introduction

Pass Transistors Transistors can be used as switches 1: Circuits & Layout

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well 1: Circuits & Layout

Tristates Tristate buffer produces Z when not enabled EN A Y Z 1 Z 1 1: Circuits & Layout

Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y 1: Circuits & Layout

Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output 1: Circuits & Layout

Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1 X 1 1: Circuits & Layout

Gate-Level Mux Design How many transistors are needed? 20 1: Circuits & Layout

Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors 1: Circuits & Layout

Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter 1: Circuits & Layout

Inverting Mux 1: Circuits & Layout

4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates 1: Circuits & Layout

D Latch When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch 1: Circuits & Layout

D Latch Design Multiplexer chooses D or old Q 1: Circuits & Layout

D Latch Operation 1: Circuits & Layout

D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop 1: Circuits & Layout

D Flip-flop Design Built from master and slave D latches 1: Circuits & Layout

D Flip-flop Operation 1: Circuits & Layout

Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition 1: Circuits & Layout

Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead 1: Circuits & Layout

Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 1: Circuits & Layout

Example: Inverter 1: Circuits & Layout

Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l 1: Circuits & Layout

Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers 1: Circuits & Layout

Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track 1: Circuits & Layout

Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track 1: Circuits & Layout

Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in l 1: Circuits & Layout

Example: O3AI Sketch a stick diagram for O3AI and estimate area 1: Circuits & Layout

Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! 0: Introduction

About these Notes Lecture notes © 2011 David Money Harris These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed. 0: Introduction