Memory Considerations

Memory Architecture: The Basics >600MHz Core >600MHz Single cycle to access 10’s of Kbytes L1 Instruction Memory L1 Data Memory L1 Data Memory >300MHz Unified L2 On-chip Off-chip Several cycles to access 100’s of Kbytes DMA <133MHz Several system cycles to access 100’s of Mbytes External Memory External Memory External Memory Unified L3 External Memory

Partitioning Data – Internal Memory Sub-Banks Multiple accesses can be made to different internal sub-banks in the same cycle Core fetch DMA Core fetch Buffer0 Buffer1 Buffer0 DMA Buffer2 Coefficients DMA Buffer1 DMA Unused Buffer2 Unused Coefficients Un-optimized DMA and core conflict when accessing sub-banks Optimized Core and DMA operate in harmony Know your memory bank architecture!

Partitioning Code and Data -- External Memory Banks Multiple rows can be “active” at the same time One row in each bank Code Video Frame 0 Code Instruction Fetch Instruction Fetch Four 16MByte Banks internal to SDRAM Video Frame 1 Ref Frame Video Frame 0 External Bus External Bus DMA DMA Unused Video Frame 1 Unused Ref Frame Row activation cycles are taken almost every access Row activation cycles are spread across hundreds of accesses External Memory External Memory

Managing External Memory Bus DMA External Memory External memory physics Must be understood Core Write Read Write Read Programmable Direction Control 2 Writes 2 Reads Improved performance with direction control Extra cycles without using direction control Group transfers in the same direction to reduce number of turn-arounds

Managing External Memory Accesses Transfer to L3 memory Blocks to L1 memory Stage line in L2 memory Turn-arounds every few transfers No Direction Control “Programmed” Direction Control Transfer directly to L3 from video peripheral Bring image block into L1 Memory (Turn-arounds occur every few transfers) Stage Video Line in L2 Memory Transfer complete line into L3 Memory Bring image block into L1 Memory (Turn-arounds are spread across hundreds of accesses)

Setting the clocks properly Try to maximize CCLK and SCLK On Blackfin Processors, CCLK can run to 600 MHz (depending on the device) SCLK is the speed of the internal system buses (max speed of 133MHz) SDRAM Refresh rate should be set to optimum value! It is based on SCLK If it is too low, you lose data because the contents “decay” If it is too high, performance suffers because the core needs to wait until the “refresh” cycles complete before an access is made