VHDL Synthesis for Implementing Digital Designs into FPGAs

Slides:

Advertisements

Similar presentations

OBJECTIVES Learn the history of HDL Development. Learn how the HDL module is structured. Learn the use of operators in HDL module. Learn the different.

Advertisements

Spartan-3 FPGA HDL Coding Techniques

Introduction To VHDL for Combinational Logic

Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi

Next in line… Advance techniques in design optimisations. Introduction to synthesis tools. Design flow using FPGA and ASIC. Summary.

History TTL-logic PAL (Programmable Array Logic)

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 1 Microcomputer Systems Design (Embedded Systems)

VLSI Design Lab Introduction

Lecture 12: Programmable Logics, HDL & VHDL Quick Recap Lecturer: Simon Winberg.

© 2011 Xilinx, Inc. All Rights Reserved Intro to System Generator This material exempt per Department of Commerce license exception TSU.

EENG 2910 – Digital Systems Design Fall Course Introduction Class Time: M9:30am-12:20pm Location: B239, B236 and B227 Instructor: Yomi Adamo

Introduction to VHDL By Mr. Fazrul Faiz Zakaria School of Computer and Communication Engineering UniMAP.

Lecture 12: Programmable Logics, HDL & VHDL Quick Recap Lecturer: Simon Winberg Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)

Chap. 1 Overview of Digital Design with Verilog. 2 Overview of Digital Design with Verilog HDL Evolution of computer aided digital circuit design Emergence.

An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008.

1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Synthesis Presented by: Ms. Sangeeta L. Mahaddalkar ME(Microelectronics) Sem II Subject: Subject:ASIC Design and FPGA.

System Arch 2008 (Fire Tom Wada) /10/9 Field Programmable Gate Array.

Tutorial 1 Combinational Logic Synthesis. Introduction to VHDL VHDL = Very high speed Hardware Description Language VHDL and Verilog are the industry.

VHDL Introduction. V- VHSIC Very High Speed Integrated Circuit H- Hardware D- Description L- Language.

Copyright © 1997 Altera Corporation & 提供 What is VHDL Very high speed integrated Hardware Description Language (VHDL) –is.

Working with Xilinx Spartan 3 Embedded Systems Lab 2009.

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis Aleksandar Milenkovic

Introductory project. Development systems Design Entry –Foundation ISE –Third party tools Mentor Graphics: FPGA Advantage Celoxica: DK Design Suite Design.

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 11 High Desecration Language- Based Design.

1 Hardware Description Languages: a Comparison of AHPL and VHDL By Tamas Kasza AHPL&VHDL Digital System Design 1 (ECE 5571) Spring 2003 A presentation.

Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.

Introduction to FPGA Tools

Hardware languages "Programming"-language for modelling of (digital) hardware 1 Two main languages: VHDL (Very High Speed Integrated Circuit Hardware Description.

Digital System Design Verilog ® HDL Introduction to Synthesis: Concepts and Flow Maziar Goudarzi.

ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

1 ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 2: Introduction to VHDL February 1, 2006.

ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.

Lecture 11 Xilinx FPGA Memories Part 2

VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.

How to use ISE Dept. of Info & Comm. Eng. Prof. Jongbok Lee.

ECE 332 Digital Electronics and Logic Design Lab Lab 3 Introduction to Starter Kit ECE 332 George Mason University.

1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3.

SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.

An Introduction to Verilog: Transitioning from VHDL

Introduction to Vivado

Flopoco in LegUp Jenny deng.

Digital System Design An Introduction to Verilog® HDL

LAB #4 Xilinix ISE Foundation Tools VHDL Design Entry “A Tutorial”

B e h a v i o r a l to R T L Coding

Introduction to Programmable Logic

Topics Modeling with hardware description languages (HDLs).

Topics Modeling with hardware description languages (HDLs).

Figure 1 PC Emulation System Display Memory [Embedded SOC Software]

Algorithmic State Machine (ASM) Charts: VHDL Code & Timing Diagrams

Field Programmable Gate Array

Field Programmable Gate Array

Field Programmable Gate Array

Cryptol aided formal verification of VHDL code

Course Agenda DSP Design Flow.

RTL Style در RTL مدار ترتيبي به دو بخش (تركيبي و عناصر حافظه) تقسيم مي شود. مي توان براي هر بخش يك پروسس نوشت يا براي هر دو فقط يك پروسس نوشت. مرتضي صاحب.

Hardware Description Languages

Lecture 18 X: HDL & VHDL Quick Recap

Lecture 1.3 Hardware Description Languages (HDLs)

Computer Architecture

HDL Hardware Description Language

VHDL Introduction.

Founded in Silicon Valley in 1984

Win with HDL Slide 4 System Level Design

CS 153 Logic Design Lab Professor Ian G. Harris

H a r d w a r e M o d e l i n g O v e r v i e w

Digital Designs – What does it take

Presentation transcript:

VHDL Synthesis for Implementing Digital Designs into FPGAs MSc Cristian Sisterna UNSJ

V H D L Very High Speed ICs Hardware Description Language Introduction C. Sisterna DSDA - © 2019

Hardware Description Language HDL (VHDL/Verilog) FPGA ASIC Xilinx Altera Lattice Actel DSDA - © 2019 C. Sisterna

Hardware Description Language High level of abstraction Easy to debug Parameterized designs Re-uso IP Cores (free) available if(reset=‘1’) then count <= 0; elsif(rising_edge(clk)) then count <= count+1; end if; DSDA - © 2019 C. Sisterna

What is not VHDL Verilog o VHDL IS NOT A programming language; IT IS A HARDWARE DESCRIPTION LENGUAGE Verilog o VHDL is not (yet) a highly abstract language: y(n) = 0.75y(n-1) + 0.3x(n) ; (Simulink/FPGA design flow) DSDA - © 2019 C. Sisterna

HDL Synthesis Sub-Set VHDL VHDL Synthesizable Used to write code to simulate the behavior of a design VHDL VHDL Synthesizable Used to implement the design into hardware (for instance in FPGA) DSDA - © 2019 C. Sisterna

VHDL ‘Description’ Examples if(sel=‘1’) then z <= y; else z <= x; end if; z y 1 sel z <= y when sel=‘1’ else x; DSDA - © 2019 C. Sisterna

VHDL ‘Description’ Ejemplos if(clk )then q <= d; else q <= q; end if; q d clk if(clk )then q <= d; end if; if(rising_edge(clk))then q <= d; end if; DSDA - © 2019 C. Sisterna

VHDL – Module Structure ff.vhd libraries& packages entity q d I/O clk architecture functionality DSDA - © 2019 C. Sisterna

VHDL Module Structure q d clk ff.vhd entity ff is port( library ieee; useieee.std_logic_1164.all; entity ff is port( d,clk : in std_logic; q : out std_logic); end ff; entity f port( end ff; architecture test of ff is begin process(clk) end process; end test; architecture test of ff is begin process(clk) if(rising_edge(clk)) then q <= d; end if; end process; end test; q d clk DSDA - © 2019 C. Sisterna

VHDL Code – Is it really Works? ? Test Bench Unit Under Test Stimulus Signals Tested Signals DSDA - © 2019 C. Sisterna

VHDL – Simulation / Verification C. Sisterna DSDA - © 2019

VHDL -> Synthesis and P&R with tmp select j <= w when “1000”, x when “0100”, y when “0010”, z when “0001”, '0‘when others; VHDL Code Design Constraints FPGA list of Components and Connections NET CLOCK PERIOD = 50 ns; NET LOAD LOC = P Synthesis – P&R Tool FPGA Library of Components Cyclone Spartan Design Attributes attribute syn_encoding of my_fsm: type is “one-hot”; DSDA - © 2019 C. Sisterna

Generic VHDL-FPGA Design Flow DSDA - © 2019 C. Sisterna ICTP - 2009

Design Implemented in the FPGA DSDA - © 2019 C. Sisterna

FPGA Kit – DE1-SoC http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=1 DSDA - © 2019 C. Sisterna

FPGA Kit – DE2-115 http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=502 DSDA - © 2019 C. Sisterna

FPGA Kit – DE0-Nano-SoC Kit http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941 DSDA - © 2019 C. Sisterna

FPGA Kit – DE0-Nano Kit http://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=139&No=593 DSDA - © 2019 C. Sisterna

FPGA – Xilinx V5 DSDA - © 2019 C. Sisterna