ASD-TDC joint test with MDT-CSM Yuxiang Guo

Outline TDC v1 (U of M) - ASD (MPI) joint test with MDT-CSM: run in legacy serial interface (80Mbps, AMT data format) trigger mode/ triggerless mode edge mode/ pair mode Amplifier, Shaper, Discriminator Time-to-Digital Converter Width (Pair Mode) 01011101… ASD chnl TDC chnl Stacked Mezz for ASD and TDC Arrival Time

TDC run status TDC v1 JTAG configuration for TDC from CSM: works JTAG configuration for ASD from TDC: works Legacy serial data interface: works in 80Mbps, compatible to CSM Trigger mode: pair and edge mode work Triggerless mode: pair and edge mode work Issues found: Legacy serial data interface: parity bit error found in logic, to be corrected in next version

Test Setup MDT CSM Width (Pair Mode) Signal Generator ASD chnl TDC chnl MDT CSM Pulse Width Test Keysight 33600A Signal Generator ASD chnl*2 TDC chnl*2 Delay (Edge/Pair Mode) Delay Time Test Signal Generator Keysight 33600A Pulse Parameter: Pulse width: 5ns Polarity: negative Amplitude: 1mv minimum Leading edge:2.9 ns Trailing edge:2.9 ns Multi ground cable to improve signal generator – mezz ground connection; Metal case for electromagnetic shielding.

Trigger/Triggerless data decode Triggerless pair mode: Trigger edge mode: mode width edge edge type edge Data_word Data_decode Data_word Data_decode From AMT3 mannual

Pulse Width Test Input Pulse for ASD: 5ns, 1~10mV, triggerless mode, pair mode ASD config: rundown current =2, main threshold=200mV, int gate=4 1mV input width hist Transfer Curve 5mV input width hist Resolution

Pulse Width Test (Different Gain) Input Pulse for ASD: 5ns, 2mV, triggerless mode, pair mode ASD config: rundown current =0~7, main threshold=200mV, int gate=4 Different Charge Gain Output Resolution

Delay Time Test (edge) Test Setup: trigger mode, edge mode, 2 input channels ASD config: rundown current =0, main threshold=200mV, int gate=3 Delay test result 0~15 ns input delay result (2 channel output and difference)

Delay Time Test (pair) Test Setup: trigger mode, pair mode, 2 input channels ASD config: rundown current =0, main threshold=200mV, int gate=3 0 ns input delay result (2 channel output and difference) Delay test result 20 ns input delay result (2 channel output and difference)

Noise rate test(HV off, 10KHz random trigger, -43mV threshold) Same rundown current, Same int gate Old ASD HV off new ASD HV off Similar performance with old ASD except 1 noisy channel

Noise rate test(HV on, 10KHz random trigger) Old ASD HV on new ASD HV on Similar with HV off. Electronic noise mainly.

Summary JTAG configuration works for both ASD and TDC with MDT-CSM; TDC legacy mode (80Mbps) works with MDT-CSM; Trigger/Triggerless mode works; Pair/Edge mode works; In legacy mode, pairty bit is reversed in pair mode, and wrong in edge mode (found design error in logic, will be corrected in next design; ASD charge gain is higher than the old one under same configuration.