All-Synthesizable 6Gbps Voltage-Mode Transmitter for Serial Link

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Presentation transcript:

All-Synthesizable 6Gbps Voltage-Mode Transmitter for Serial Link Young-Ho Choi, Kihwan Seong, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park Department of Electrical Engineering POSTECH, Pohang, Korea

Outline Motivation − Fully synthesizable transmitter Proposed voltage-mode TX − With 2-tap FFE Measurement results Conclusion

Motivation Advantages of the synthesizable circuit − Good portability with process − High compatibility with other digital blocks Fully synthesized circuits are implemented − ADCs − PLLs − CDRs There is no high-speed synthesizable TX

Transmitter output driver <Current mode driver> Difficult to implement CM driver using digital std. cells

Tri-state inverter cell Conv. voltage mode driver 6Gbps synthesizable TX Tri-state inverter cell Conv. voltage mode driver Voltage mode driver is suitable for digital synthesis The inverter with source R replaced by tri-state inverter

Requirements for 6Gbps synthesizable TX A branch of differential TX driver Output impedance matching @ out = ‘0’ by adjusting # of parallel tri-state inverter cells 2-tap feed-forward equalization(FFE) for 20dB loss channel

Output impedance calibration A 1/10 replica used for impedance matching @ output = ‘0’ After calibration, pull-down resistor of main driver Rn.M ≈ 50

Non-linearity of pull-down DR Pull-down driver I-V characteristic of pull-down driver

Effect of non-linearity of pull-down DR Conventional driver Proposed driver RT = 50 Ohm, TX pin C = 1.7pF L=2.5nH, RX pin C = 1.7pF L=2.5nH No appreciable difference between proposed and conventional drivers

All-synthesizable 2-tap FFE 6Gbps FF not used for 1T delay, because it cannot be implemented by synthesis

DLL for 1T delay generation For DLL operation, training patterns are used (1010…) 1T = (delay of coarse delay line + delay of fine delay line)

Proposed 2-tap FFE driver with 2-to-1 serializer

Final proposed all-synthesizable voltage-mode TX

Chip photo and layout • 65nm CMOS process • Chip area : 210 x 226 um2

Measurement setup

Measured eye-diagram (6Gbps) TX output RX input PRBS-7 PRBS-31 EQ : 1001

Performance summary

Conclusion 6Gbps voltage-mode TX synthesized with 2-tap FFE Wide eye-opening achieved @ 1.4m FR4 channel 1-bit-period delay generation circuit for FFE because 6Gbps F/F cannot be implemented by synthesis

Thank you!!